A 3D stacked system-in-package (SiP) with a widebus structure is expected to have large SSO noise compared with conventional memory devices with small number of IOs. Then, Power supply impedances for a 3D SiP with a widebus structure has been investigated including stacked chips, an organic substrate, and a board. The 3D SiP consisted of 3 stacked chips and an organic substrate. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic substrate, whose size was 26 mm by 26mm. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.) and confirmed by measurement. Then, the PDN impedance for the organic substrate was extracted by using SIwave (Ansys Inc.) and also confirmed by measurement. Finally, the total PDN impedance seen from each chip was synthesized to estimate the power supply disturbance due to the anti-resonance peak, and power supply noise level was estimated by establishing a whole SPICE model. IntroductionRecently, three dimensionally stacked system-in-package (3D SiP) has been extensively developing for the next generation higher density system applications.[1]-[3] Stackedchip technology was initially developed by using wire-bonding for cellular phone application, because conventional 2D structure occupies larger space. However, wire-bonding is not so good from the electrical performance point of view due to larger inductance of wire. Through silicon via (TSV)-based 3D SiP is the most promising technology to enable higher density and better electrical performance, because TSV's connect vertically among stacked chips as short as possible. Furthermore, 3D SiP with TSV provides more flexibility in assembly, and the number of connections can be easily increased than wire-bonded 3D SiP does.Power distribution among the stacked chips depends on the number of power/ground TSV's and the decoupling capacitance of the stacked chips and so on. However, little papers have been published regarding to the design methodology of power distribution network (PDN) for 3D SiP.[4]- [7] In this paper, 3D SiP, consisted of a logic chip, a silicon interposer, a logic chip, and an organic substrate, has been designed and fabricated. Then, the PDN impedances for three chips and organic package substrate were measured by vector network analyzer and simulated using commercially available software's. Then, the total PDN impedances were synthesized to estimate the impact on simultaneous switching output (SSO)
Power supply impedance and simultaneous switching output (SSO) noise for a 3D system-in-package (SiP) with a wide bus structure have been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, these 3 stacked chips were assembled on the organic package substrate, whose size was 26 mm by 26 mm. The 3D stacked SiP with a widebus structure was estimated to have large SSO noise compared with conventional memory devices with small number of I/O s. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.).Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.
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