Abstract:Power supply impedance and simultaneous switching output (SSO) noise for a 3D system-in-package (SiP) with a wide bus structure have been investigated. The 3D SiP consisted of 3 stacked chips and an organic package substrate. These three chips were a memory chip on the top, Si interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. Next, these 3 … Show more
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