Chip-Level Simultaneous Switching Current Measurement in Power Distribution Network Using Magnetically Coupled Embedded Current Probing Structure

Kim, Jonghoon J.; Cho, Changhyun; Bae, Bumhee; Kim, Suk Jin; Kong, Sunkyu; Kim, Heegon; Jung, Daniel; Kim, Jiseong

doi:10.1109/tcpmt.2014.2362130

Cited by 9 publications

(3 citation statements)

References 15 publications

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“…In other words, Iinjected in the frequency domain is equal to Vinduced in frequency domain divided by ZT. Lastly, Iinjected in frequency domain is converted back to time domain waveform using the Inverse Fast Fourier Transform (IFFT) [2]. As a result, we can finally obtain the original current waveform, which was injected through the center TSVs.…”

Section: Design Of the Tsv-based Current Probe (Tcp)mentioning

confidence: 99%

“…However, as the group of vertically connected logic ICs operate simultaneously as shown in Fig. 1, a large simultaneous switching current (SSC) can create substantial simultaneous switching noise (SSN) on power nets, causing a number of signal integrity and power integrity problems including deteriorated noise and timing margins; especially, with continuously decreasing operating voltage for mobile applications, susceptibility to SSN keeps on increasing [1] [2]. Methods to accurately predict the SSN would allow better determination of maximum timing and noise margins, as well as better assessment of noise mitigation techniques.…”

Section: Introductionmentioning

confidence: 99%

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TSV-based current probing structure using magnetic coupling in 2.5D and 3D IC

Kim

Jung

Kim

et al. 2015

2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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Simultaneous switching noise (SSN) is caused by the simultaneous switching of a group of I/O drivers, and isproportional to the total inductance and the rate of change of the switching current. This often leads to signal distortion and degradation of signal and power integrity of systems. Furthermore, with the continuously decreasing operating voltage, susceptibility to SSN keeps on increasing and it becomes increasingly challenging to achieve high performance interfaces. Therefore, it is highly important to perform SSN analysis in order to accurately investigate the noise and timing margin of the devices under test; hence, it is important to know the exact amount of switching current drawn by the ICs. In this paper, we propose TSV-based current probing structure using magnetic coupling, named TSV-based Current Probe (TCP). By capturing the magnetic flux induced by the injected current and processing it through a series of reconstruction steps, we can obtain the original current waveform of interest. Through a series of simulations in frequency and time domains, we verify the performance of the proposed probing structure, TCP. Lastly, TCP is fabricated using TSV fabrication techniques and measured for experimental verification.

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Section: Design Of the Tsv-based Current Probe (Tcp)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

TSV-based current probing structure using magnetic coupling in 2.5D and 3D IC

Kim

Jung

Kim

et al. 2015

2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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“…1, there are various types of disconnection defects in TSV-based 3D-IC that can severely degrade the electrical performance of the system by impeding the signal transmission. However, conventional testing methods of wafer-level testing have exhibited many limitations, such as pitch limitation of the conventional probe cards, physical damage on microbumps, and height variation of the microbumps from unstable TSV fabrication process [3].…”

Section: Introductionmentioning

confidence: 99%

Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling

Kim¹,

Kim²,

Kim³

et al. 2013

2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)

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Driven by the abrupt miniaturization of mobile devices and demand for 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating multiple dies of various functions as a whole system. However, due to the instability in the TSV fabrication process, various types of disconnection defects can be resulted during fabrication steps, resulting in a severe decrease in the final chip yield as the number of TSVs and stacked dies increases. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure using capacitive coupling that can detect TSV disconnection defects on wafer-level. The proposed structure can detect the TSV disconnection by observing the change in the capacitance between adjacent TSVs, using only passive components such as metal pads and lines, without additional power consumption for the testing. Through time-and frequency-domain simulation results, such as transfer impedance and voltage waveforms, we verified that the proposed structure can successfully detect TSV defects, while overcoming the limitations of the conventional direct probing methods.

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