Design of contactless wafer-level TSV connectivity testing structure using capacitive coupling

Abstract

Driven by the abrupt miniaturization of mobile devices and demand for 3D-IC, Through Silicon Via (TSV) has been highlighted as the key technology for compactly integrating multiple dies of various functions as a whole system. However, due to the instability in the TSV fabrication process, various types of disconnection defects can be resulted during fabrication steps, resulting in a severe decrease in the final chip yield as the number of TSVs and stacked dies increases. In this paper, we propose a novel contactless wafer-level TSV connectivity testing structure using capacitive coupling that can detect TSV disconnection defects on wafer-level. The proposed structure can detect the TSV disconnection by observing the change in the capacitance between adjacent TSVs, using only passive components such as metal pads and lines, without additional power consumption for the testing. Through time-and frequency-domain simulation results, such as transfer impedance and voltage waveforms, we verified that the proposed structure can successfully detect TSV defects, while overcoming the limitations of the conventional direct probing methods.