Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration

Noguera, Juanjo; Kennedy, Irwin O.

doi:10.1109/fpl.2007.4380654

Cited by 42 publications

(17 citation statements)

References 5 publications

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“…There are several reports regarding the energy-and areasaving effect of DPR [1], [2], but the effectiveness of DPR in 28-nm process FPGA has not been clarified yet. Therefore, we investigate the power consumption of a DPR system by developing a real DPR application on the 28-nm Kintex-7 [3].…”

Section: Introductionmentioning

confidence: 99%

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Hori

Katashita

Kobara

2013

2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)

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We empirically evaluated the energy-and areasaving effect of Dynamic Partial Reconfiguration (DPR) of a 28-nm process FPGA. DPR is a technology where a portion of the entire circuit is replaced with another one, while the other parts of the circuit still continue running. Using DPR, different functionalities are not necessarily implemented at once; only required modules need be implemented on the FPGA. Therefore, a DPR system requires less hardware resources, and consequently, can save the power consumption of the system. We explored the effectiveness of DPR in saving energy and area of a multi-algorithm cryptoprocessor on Kintex-7 FPGA on SASEBO-GIII board. The cryptoprocessor supports the six ISO/IEC 18033-3 block cipher algorithms: AES, Camellia, SEED, TDEA, MISTY1, and CAST-128. In a DPR cryptoprocessor, only one cipher module is implemented at once, and it is overwritten when a different algorithm is required. Compared to the non-DPR cryptoprocessor, the DPR cryptoprocessor can reduce up to 74% hardware resource (slice) and 3.4% energy consumption.

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Section: Introductionmentioning

confidence: 99%

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Hori

Katashita

Kobara

2013

2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE)

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“…For example, in many communication systems a forward error correction code core (i.e., Viterbi decoder, Solomon coder, cyclic coder, etc.) is widely used [5]. This core comes in several implementations which vary in throughput.…”

Section: Introductionmentioning

confidence: 99%

Lowering power consumption using run-time reconfiguration for stereo rectification

Islam

Chun

MacLean

et al. 2008

2008 Canadian Conference on Electrical and Computer Engineering

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Trends of high power usage in portable consumer electronics and high speed designs is an important factor that biases the selection of an ASIC over a FPGA. ASICs are optimized to minimize the amount of logics used for a particular application; reductions in power are noticed when compared against FPGAs design for the same application. On the other hand, some FPGAs equipped with run-time reconfiguration, allow portions of the design to be changed on the fly. Having an appropriate methodology which creates a micro-level static architecture and reduces the reconfiguration overhead is used to lower the power consumption. This can allow the FPGA designs to be somewhat competitive against ASIC designs. This paper explores the reconfiguration methodology to lower the power consumption for the application of stereo rectification. The results obtained show significant savings in logical resources and power consumption when compared to ASIC-like FPGA implementations.

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“…Several system design solutions can be found in FPGA literature for such novel architectures. Improvements in speed of partial reconfiguration technology and advancements in software tools[10] by industrial FPGA providers such as Xilinx [2], Altera, and Atmel have spurred intense interest in hardware virtualization. Reduction in reconfiguration time in successive FPGA chip generations favors broader hardware virtualization inclusion in future reconfigurable architectures.…”

Section: Introductionmentioning

confidence: 99%

“…Hardware virtualization is actively pursued in current research [1], [2] for programmable devices such as FPGA and CPLD. Literature survey reveals extensive research exploiting virtualization techniques for improving logic density [3], partial bitstream generation, time multiplexed system design [4] and novel reconfigurable architectures [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Partial reconfiguration logic synthesis by temporal slicing

Ponpandi

Tyagi

2011

2011 International Conference on Field-Programmable Technology

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Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set to optimize the hardware circuit for reduction in area. We show that reduced area dynamic reconfigurable slices can be generated for combinational circuits with minimal effect on the critical path. The results reported for MCNC logic synthesis benchmark circuits show an average 40% reduction in area for logic slices.

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Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration

Cited by 42 publications

References 5 publications

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Lowering power consumption using run-time reconfiguration for stereo rectification

Partial reconfiguration logic synthesis by temporal slicing

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