Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA

Hori, Yohei; Katashita, Toshihiro; Kobara, Kazukuni

doi:10.1109/gcce.2013.6664803

Cited by 3 publications

(3 citation statements)

References 5 publications

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“…The proposed DPR architecture, on the other hand, shows comparable performance with the DPR architectures of refs [27,28,30]. In terms of area, the proposed reconfigurable…”

Section: Fpga Implementation-results and Analysismentioning

confidence: 86%

“…Moreover, the repetitive-loop structure results in a low throughput value of 130.2 Mbps and in-turn the high-power consumption [15][16][17][18][19][20][21][22][23][24][25][26]. Studies on static reconfigurable cryptographic modules have also been proposed for SNOW / ZUC algorithms and AES / KASUMI / SNOW / ZUC algorithms signifying flexible implementations [14,[27][28][29][30][31][32][33][34][35][36].…”

Section: Introductionmentioning

confidence: 99%

“…The DPR technology employing AES, TDEA, MISTY1, CAMELLIA, SEED and CAST-128 has also been reported in representing power efficient design. In addition, the technique has also been employed to implement the variants of AES i.e., AES-128 / 192 and 256 bits [27,28,30].…”

Section: Introductionmentioning

confidence: 99%

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On the dynamic reconfigurable implementations of MISTY1 and KASUMI block ciphers

Jiexian,

Khizar,

Ali

et al. 2023

PLoS ONE

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Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables—RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.

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“…The proposed DPR architecture, on the other hand, shows comparable performance with the DPR architectures of refs [27,28,30]. In terms of area, the proposed reconfigurable…”

Section: Fpga Implementation-results and Analysismentioning

confidence: 86%