Partial reconfiguration technology of programmable devices, such as FPGA, enables the virtualization of hardware circuit by temporal multiplexing of active parts (logic slices). An immediate consequence of virtualization is the increase in cardinality of the don't care set associated with a logic slice. In this paper, we present a logic slicing methodology that exploits the enhanced don't care set to optimize the hardware circuit for reduction in area. We show that reduced area dynamic reconfigurable slices can be generated for combinational circuits with minimal effect on the critical path. The results reported for MCNC logic synthesis benchmark circuits show an average 40% reduction in area for logic slices.
In mobile devices, user satisfaction with the UI interactions ought to be the primary design driver. Some recent research has integrated a saturating, non-linear user satisfaction function in thread scheduler. Mobile embedded systems are moving towards large systems on chip (SoCs) with a Network on Chip (NoC). The inter-thread communication in such a system is hosted by the NoC as a flow. The application and operating system level user satisfaction research assumes that the throughput of inter-thread edges is limited only by the computational constraints of the nodes. With NoC, however, NoC resource allocation policies play an important role in the application level user satisfaction. In this paper, we filter down the user satisfaction from an application level attribute to the routers to improve the QoS at the routing level in order to leverage the user satisfaction at the application and system level. We demonstrate that this technique improves the user satisfaction of MP3 application by 10% while maintaining the QoS guarantee of MPEG-2 application.
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