Power-performance modeling on asymmetric multi-cores

Abstract

Asymmetric multi-core architectures have recently emerged as a promising alternative in a power and thermal constrained environment. They typically integrate cores with different power and performance characteristics, which makes mapping of workloads to appropriate cores a challenging task. Limited number of performance counters and heterogeneous memory hierarchy increase the difficulty in predicting the performance and power consumption across cores in commercial asymmetric multi-core architectures. In this work, we propose a software-based modeling technique that can estimate performance and power consumption of workloads for different core types. We evaluate the accuracy of our technique on ARM big.LITTLE asymmetric multi-core platform.

An empirical validation of power-performance scaling: DVFS vs. multi-core scaling in big.LITTLE processor

“…Pricopi et al presented powerperformance model in asymmetric multi-core using big-little core in [11]. However, their model is evaluated with single-core-per-cluster.…”

Performance Modeling of Multithreaded Programs for Mobile Asymmetric Chip Multiprocessors

“…A program's "signature" on architectural resources can be used to select models for different core types [17]. Recent work extended PIE with compiler assistance to estimate cycles per instruction [4]. Unlike MONARCH, these efforts did not address scalability and core bias of multithreaded programs.…”

“…Statistical models, similar to our approach, have been used to predict performance [9], [10], [16], [4]. Using HPC, analytic models have been developed to guide migration between core types [5].…”

“…One approach executes a program on all core types to measure relative performance for picking the type that achieves performance and power goals [2], [3]. Recent work uses analytic and experimental models [4], [5], [6], [7]. Performance Impact Estimation is a state-of-the-art analytic model to select core type [5].…”

Energy-efficient computing with heterogeneous multi-cores

“…As an application is running on one core type, we would like to predict its power, performance behavior on the other core types and at different voltage-frequency levels so as decide whether the application should be migrated and to where. We develop such a powerperformance model for ARM big.LITTLE architecture [10]. This modeling is challenging for a real architecture for various reasons.…”