Power issues related to branch prediction

Parikh, Dharmesh; Skadron, Kevin; Zhang, Yan; Barcella, Mary Lashley; Stan, Mircea R.

doi:10.1109/hpca.2002.995713

Cited by 87 publications

(72 citation statements)

References 29 publications

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“…Usually, branch instructions are about 20% of the total executed instructions [3,17]. The idea of accessing the predictor modules only on branch instructions can reduce the total predictor power up to 80% [12]. The crucial point is that, in order to avoid a predictor access for no-branch instructions, it is necessary to know whether the fetched instruction will be a branch, while, at this time, the undecoded instruction is still in cache, so either we rely on a predecoded bits stored in cache, or we wait for the branch is fetched and then we decode it.…”

Section: Low-power Optimizationmentioning

confidence: 99%

“…An effective technique to obtain good power-performance trade-offs consists of reducing predictor lookups by avoiding no-branch instructions to access the branch prediction unit [12,14]. Usually, branch instructions are about 20% of the total executed instructions [3,17].…”

Section: Low-power Optimizationmentioning

confidence: 99%

“…In [12], the authors analyze several branch prediction organizations for superscalar processors from the power/performance perspective. The authors found that, to reduce the energy consumption of the processor, it is worthwhile to spend more power on the branch predictor module.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

et al. 2005

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Section: Low-power Optimizationmentioning

confidence: 99%

Section: Low-power Optimizationmentioning

confidence: 99%

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Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

et al. 2005

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“…Research [8] [3] has shown that, even with their increased power cost, modern larger predictors actually save global power by the effects of their increased accuracy. This means that any attempt to reduce the power consumption of a dynamic predictor must not come at the cost of decreased accuracy; a holistic attitude to processor power consumption must be employed [7] [9].…”

Section: Introductionmentioning

confidence: 99%

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

Hicks

Egan

Christianson

et al. 2006

Advances in Computer Systems Architecture

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Abstract. Dynamic branch predictor logic alone accounts for approximately 10% of total processor power dissipation. Recent research indicates that the power cost of a large dynamic branch predictor is offset by the power savings created by its increased accuracy. We describe a method of reducing dynamic predictor power dissipation without degrading prediction accuracy by using a combination of local delay region scheduling and run time profiling of branches. Feedback into the static code is achieved with hint bits and avoids the need for dynamic prediction for some individual branches. This method requires only minimal hardware modifications and coexists with a dynamic predictor.

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“…They introduced banking to reduce the active portion of the predictor. They also introduced prediction probe detector (PPD) to identify when a cache line has no branches so that a lookup in the predictor buffer/BTB can be avoided [9].…”

Section: Related Workmentioning

confidence: 99%

A Power-Aware Alternative for the Perceptron Branch Predictor

Aasaraai

Baniasadi

Advances in Computer Systems Architecture

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Abstract. The perceptron predictor is a highly accurate branch predictor. Unfortunately this high accuracy comes with high complexity. The high complexity is the result of the large number of computations required to speculate each branch outcome.In this work we aim at reducing the computational complexity for the perceptron predictor. We show that by eliminating unnecessary data from computations, we can reduce both predictor's power dissipation and delay. We show that by applying our technique, predictor's dynamic and static power dissipation can be reduced by up to 52% and 44% respectively. Meantime we improve performance by up to 16% as we make faster prediction possible.

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Power issues related to branch prediction

Cited by 87 publications

References 29 publications

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

Reducing the Branch Power Cost in Embedded Processors Through Static Scheduling, Profiling and SuperBlock Formation

A Power-Aware Alternative for the Perceptron Branch Predictor

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