Power grid physics and implications for CAD

Pant, Sanjay; Chiprout, Eli

doi:10.1145/1146909.1146964

Cited by 92 publications

(32 citation statements)

References 11 publications

(9 reference statements)

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“…The current distribution in present chips tends to be locally uniform and globally nonuniform. This property is referred as spatial locality and is utilized in power grid design [17]- [19]. Because sleep transistors act as switches between the virtual and chip's power/ground network, the current to each logic cell is supplied by sleep transistors in its vicinity.…”

Section: (C) the Location (500500) Is Chosen As The Root Of The Kd-mentioning

confidence: 99%

Early detection of current hot spots in power gated designs

Sengupta¹,

Ergin²,

Veneris³

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-With the growing popularity of hand-held batterypowered devices, leakage power is a major concern in the nanometer CMOS era. Power gating technique is an effective and widely adopted solution to this problem. The challenge of implementing power gating is the sizing and placement of the sleep transistors that are used to gate the power supply. In a placed design, due to non-uniform current demand of logic cells, some regions of the chip can have sleep transistors with very high current demand, causing power grid noise violations. Identifying these regions early in the design cycle is critical to the success of power gating implementation. This paper presents a novel methodology to calculate the current demand of each sleep transistor and locate regions in the chip where multiple sleep transistors experience very high current demand. In this paper, we model the spatial locality of the current drawn by each logic cells in the form of a bounding box. We explore techniques to identify the appropriate size of the bounding boxes. Furthermore, we extend the current distribution technique to handle placement blockages that do not share the sleep transistor network of the chip. Experimental results on industrial circuits show that the proposed algorithm can identify over 90% of such regions with a 20x run-time reduction compared to state-of-the-art commercial CAD tool.

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Section: (C) the Location (500500) Is Chosen As The Root Of The Kd-mentioning

confidence: 99%

Early detection of current hot spots in power gated designs

Sengupta¹,

Ergin²,

Veneris³

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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“…1) [20,21]. The horizontal and vertical segments of a grid are routed at different metal levels (e.g.…”

Section: On-chip P/g Network Modelmentioning

confidence: 99%

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Liu

Wang

et al. 2009

2009 IEEE Computer Society Annual Symposium on VLSI

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Power gating induced power/ground (P/G) noise is a major reliability problem facing by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large P/G noise and can cause timing divergence and even functional errors in surrounding processing units. P/G noise is different from thermal or energy which is an accumulative effect. The noise level should be predicted and victim circuits should be protected before the noise is induced. Hence, the power gating-aware scheduling problem with the consideration of P/G noise should be solved using an on-line method considering the run-time variation of tasks' execution time. In this paper, we formulate an on-line task scheduling problem with the consideration of P/G noise based on our detailed P/G noise analysis platform for MPSoC. An efficient on-line Greedy Heuristic (GH) algorithm that adapts well to real-time variations is proposed to reduce noise protection penalty and improve MPSoC performance. Our experiments show that the algorithm can achieve on average 26% performance improvement together with on average 73% noise protection penalty saving compared with the conservative stop-go method. We also compare our technique with a twostep solution that computes a static schedule at compile time and make adjustment on the schedule according to runtime variations. For benchmark with larger task number, GH method achieves impressive performance improvement comparing with the two-step solution.

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“…With technology scaling, power supply voltages become lower, clock rates rise, and greater functionality is integrated on-chip, significantly increasing the power dissipation [1], [2]. Faster transition times and higher current demands produce larger voltage droop due to resistive IR and inductive L di/dt noise [3].…”

Section: Introductionmentioning

confidence: 99%

“…The number of on-chip power supplies is increasing, requiring innovative design methodologies to satisfy stringent noise and power constraints of these high complexity integrated circuits [1], [2]. Placing the power supply on-chip eliminates losses due to the parasitic impedances of the package , improving the quality of the delivered power [6].…”

Section: Introductionmentioning

confidence: 99%

Distributed power network co-design with on-chip power supplies and decoupling capacitors

Köse

Friedman

2011

International Workshop on System Level Interconnect Prediction

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Abstract-With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

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Power grid physics and implications for CAD

Cited by 92 publications

References 11 publications

Early detection of current hot spots in power gated designs

Early detection of current hot spots in power gated designs

On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise

Distributed power network co-design with on-chip power supplies and decoupling capacitors

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