Distributed power network co-design with on-chip power supplies and decoupling capacitors

Abstract

Abstract-With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

Design methodology to distribute on-chip power in next generation integrated circuits

“…The required supply voltage levels and the noise constraints vary significantly for different technologies. Novel voltage regulator topologies [4]- [10] have recently been proposed, enabling not only on-chip power supply integration but also multiple on-chip point-of-load power supplies [10], [11]. These on-chip point-of-load power supplies provide the required voltage close to the load circuits, greatly reducing the effective impedance between the load circuits and power supplies [12].…”

“…The interactions between the power supplies and the decoupling capacitors are, however, not considered, which can significantly affect the performance of an integrated circuit [17]. These interactions are quite critical in producing a robust power distribution network [10]. Decoupling capacitors and on-chip power supplies exhibit several distinct characteristics such as the response time, area requirements, and parasitic output impedance.…”

Distributed power delivery for energy efficient and low power systems

“…The required supply voltage levels and the noise constraints vary significantly for different technologies. Novel voltage regulator topologies [4]- [10] have recently been proposed, enabling not only on-chip power supply integration but also multiple on-chip point-ofload power supplies [10]- [12]. These on-chip point-of-load power supplies provide the required voltage close to the load circuits, greatly reducing the effective impedance between the load circuits and power supplies [13].…”

“…The interactions between the power supplies and the decoupling capacitors are, however, not considered, which can significantly affect the performance of an integrated circuit [18]. These interactions are quite critical in producing a robust power distribution network [10]. Decoupling capacitors and on-chip power supplies exhibit several distinct characteristics such as the response time, area requirements, and parasitic output impedance.…”

Effective Resistance of a Two Layer Mesh

“…Manuscript received December 21, 2010 The effective resistance of a mesh is used in power grid analysis [5], [6], substrate analysis [7], decoupling capacitance allocation [8]- [11], power dissipation [12] and electrostatic discharge (ESD) analysis [12], and measuring resistance variations in power distribution networks [13]. The effective resistance is used to determine the effective region of a decoupling capacitor [8], [14].…”