Power estimation approach for SRAM-based FPGAs

Weiss, K.; Oetker, Carsten; Katchan, Igor; Steckstor, T.; Rosenstiel, Wolfgang

doi:10.1145/329166.329207

Cited by 19 publications

(16 citation statements)

References 1 publication

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“…[Shang02] analyzed the dynamic power consumption for Xilinx Virtex-II FPGA family. [Weiß00] presented the power consumption for Xilinx Virtex architecture using their emulation environment. All the above work was targeted at specific architectures but did not provide any insight into how the architecture parameters affect FPGA power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Architecture evaluation for power-efficient FPGAs

Chen

et al. 2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays

140

135

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This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contributions: (i) We develop a mixed-level FPGA power model that combines switch-level models for interconnects and macromodels for LUTs; (ii) We develop a tool that automatically generates a back-annotated gate-level netlist with post-layout extracted capacitances and delays; (iii) We develop a cycleaccurate power simulator based on our power model. It carries out gate-level simulation under real delay model and is able to capture glitch power; (iv) Using the framework fpgaEVA-LP, we study the power efficiency of FPGAs, in 0.10um technology, under various settings of architecture parameters such as LUT sizes, cluster sizes and wire segmentation schemes and reach several important conclusions. We also present the detailed power consumption distribution among different FPGA components and shed light on the potential opportunities of power optimization for future FPGA designs (e.g., ≤ 0.10um technology).

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Section: Introductionmentioning

confidence: 99%

Architecture evaluation for power-efficient FPGAs

Chen

et al. 2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays

140

135

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“…Kussey and Rabaey [2] used a Xilinx XC4003 FPGA test board to measure power and reported a power breakdown for FPGA components. Weill [3] presented the power consumption for Xilinx Virtex architecture using an emulation environment. Both of the work was carried out for specific industrial FPGA architectures.…”

Section: China Postdoctoral Science Foundation Funded Projectmentioning

confidence: 99%

A novel power estimation framework for SRAM-based FPGAs

Wang

Chen

Wen

et al. 2009

2009 Asia Pacific Conference on Postgraduate Research in Microelectronics &Amp; Electronics (PrimeAsia)

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Field Programmable Gate Arrays (FPGAs) is becoming one of the most widely used electronics devices. Because of its unique architecture, power estimation is a complicated task for FPGAs. This paper presents a novel power estimation framework for SRAM-based FPGAs. Considering both dynamic power and static power, a gate-level power model for configuration logic blocks (CLBs) and a transistor-level power model for interconnect resources is developed for power estimation of SRAM-based FPGAs. To achieve the accuracy and efficiency, we use the transition density method includes glitches filtering in our proposed power estimation framework. 20 MCNC benchmark circuits have been applied to our proposed power estimation framework, and the detailed power dissipation distribution obtained from the experimental results is presented. The proposed framework is also quite flexible, which is capable of estimating power for a wide variety of SRAM-based FPGA architectures.

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“…Emulation based power estimation is proposed in [12], but the problem in this approach is that it is restricted to sequential designs.…”

Section: Related Workmentioning

confidence: 99%

“…The results of previous research efforts [8][9][10][11][12][13][14][15] encouraged FPGA vendors to provide power estimators within their commercial platforms [16][17]. The estimators work on post place-and-route (P&R) stage, so they provide accurate results, but the problem is the long time needed to reach such stage.…”

Section: Related Workmentioning

confidence: 99%

Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme

Abdelhalim

Habib

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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In this paper a fast and accurate upper-bound power consumption estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware implementation as a single alternative, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound the latency range for different hardware implementations. The presented estimation tool estimates the power consumption for these two hardware alternatives. The computational cost of the presented estimation tool depends linearly on the design complexity as no simulation processes are performed, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate. Overall power consumption estimations are within ±4% of the actual power consumed with an average of 1% error, however, Logic Elements (LEs) and clock power estimates are accurate with an average error of 7.7% and 6.5% respectively.

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Power estimation approach for SRAM-based FPGAs

Cited by 19 publications

References 1 publication

Architecture evaluation for power-efficient FPGAs

Architecture evaluation for power-efficient FPGAs

A novel power estimation framework for SRAM-based FPGAs

Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme

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