Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

Silveira, Bianca; Paim, Guilherme; Abreu, Brunno; Grellert, Mateus; Diniz, Cláudio M.; Costa, Eduardo; Bampi, Sérgio

doi:10.1109/tcsi.2017.2728802

Cited by 58 publications

(23 citation statements)

References 51 publications

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“…In this section, we review four well-established adder compressors, namely the 3-2, 4-2, 5-2 and 7-2 [10]. The current state-of-the-art hierarchical 8-2 adder compressors [6] use these compressors as building blocks.…”

Section: Adder Compressors Overviewmentioning

confidence: 99%

“…These four architectures were thoroughly explored in the context of video encoding in works [11], [12] and also [6].…”

Section: B 8-2 Hierarchical Adder Compressormentioning

confidence: 99%

“…his implies that the 1 from the adder compressor module must be used as input to the compressor + 2 and not to the compressor + 1. This scheme has the benefit of reducing the number of necessary signals in the 8-2 adder compressor from five to only three at the cost of increasing energy consumption [6]. Since this strategy was not considered in our design for the 8-2 adder compressor, a further analysis is referred to [10] and [6].…”

Section: B 8-2 Hierarchical Adder Compressormentioning

confidence: 99%

“…The use of 8-2 adder compressors can also reduce energy consumption in SAD modules, as presented in [6]. On the other hand, combinations of 8-2 with 6-2 and 4-2 adder compressors achieve energy reduction in the computation of the Discrete Tchebichef Transform, as shown in [7].…”

Section: Introductionmentioning

confidence: 99%

“…This paper explores four current state-of-the-art 8-2 adder compressor circuits [6] and proposes a novel circuit, presenting a shorter and limited signal propagation. The architectures are synthesized into a 65 nm standard cells library for operands with 9, 16, 24, 32 and 64 bits and compared for maximum operational frequency, power dissipation and circuit area.…”

Section: Introductionmentioning

confidence: 99%

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Fast Monolithic 8-2 Adder Compressor Circuit

Fontanari

Paim

Rocha³

et al. 2019

JICS

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Adder compressor architectures have been widely used in multipliers and have recently achieved improvements over conventional approaches in the computation of multiple modules, such as transform blocks, in the context of video coding. This paper reviews four different state-of-the-art 8-2 adder compressor architectures and proposes a novel one. A 65 nm commercial standard cell library was used to synthesize the compressors. The results show that, as a consequence of a shorter critical path, our circuit presented significant improvements regarding maximum operational frequency, while still maintaining similar results for power dissipation. Our circuit also managed to achieve a smaller circuit area, as a result of a more straightforward net interconnection.

show abstract

Section: Adder Compressors Overviewmentioning

confidence: 99%

“…These four architectures were thoroughly explored in the context of video encoding in works [11], [12] and also [6].…”

Section: B 8-2 Hierarchical Adder Compressormentioning

confidence: 99%

Section: B 8-2 Hierarchical Adder Compressormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Fast Monolithic 8-2 Adder Compressor Circuit

Fontanari

Paim

Rocha³

et al. 2019

JICS

Self Cite

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An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

Teja

Arunmetha

Bangalore³

2021

Concurrency and Computation

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The main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost-effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

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FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

Palanisamy

Ramachandran²

2020

Circuit Theory & Apps

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SummaryFor ultra‐low‐power applications, the computing components are smaller in size and consume less energy. In nonstationary signal analysis, the transformation plays an important role. Out of different transformation techniques, the most famous and dominant architecture is the discrete wavelet transform. The building block of the architecture should be optimized by all parameters. In this paper, the optimization was done on the power reduction and leakage current reduction. A new FinFET‐based lifting‐based wavelet architecture was proposed. Power gating and reversible logic methodology are proposed for the FinFET‐based transform to reduce the dynamic power by about 30%. The proposed FinFET‐based processing elements were utilized in the various blocks of the lifting‐based DWT architecture. The implementation was done in 32‐nm CMOS and FinFET technology. From the results, it has been investigated that the FinFET‐based circuits are efficient when compared with CMOS technology. This is due to the second‐order effects happening in CMOS circuits below 45 nm. The proposed design consumes less area and low leakage current and power when compared with the CMOS technology. Future trends of using multigate devices below 14 nm technology are presented finally.

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Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

Cited by 58 publications

References 51 publications

Fast Monolithic 8-2 Adder Compressor Circuit

Fast Monolithic 8-2 Adder Compressor Circuit

An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

FinFET‐based power‐efficient, low leakage, and area‐efficient DWT lifting architecture using power gating and reversible logic

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