Power efficient standard cell library design

Afonso, Ryan; Rahman, Mostafizur; Tennakoon, Hiran; Sechen, Carl

doi:10.1109/dcas.2009.5505245

Cited by 6 publications

(9 citation statements)

References 3 publications

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“…The standard deviation in errors are 5.3%, 2.5%, 1.9% and .9%, for 1, 2, 3 and 4 v th options, respectively (the errors are given as a percentage of the discrete optimum). In contrast, using the quantization errors in (1), (2), and (3) provide much larger errors, at 16%, 34%, 27% and 14%, respectively.…”

Section: Small Circuit Experimentsmentioning

confidence: 91%

“…This question is a stronger question than the library cell selection problem -if the suboptimality can be estimated, this procedure can be used to select a set of library cells, or even the technology that should be used to implement the design. In contrast, research on library cell selection [4,10,2] cannot estimate the suboptimality.…”

Section: Ieee/acm International Conference On Computer-aided Design (mentioning

confidence: 99%

“…They find that a ratio of 1.3 with cells of size {1×, 1.3×, 1.3 2 ×, ...} provides results very close to that with an infinite set of gate sizes. [2] provide experimental results that evaluate different types of library selection. The experiments are performed using their continuous sizing plus branch-and-bound sizing method to evaluate different sets of gate sizes.…”

Section: Ieee/acm International Conference On Computer-aided Design (mentioning

confidence: 99%

“…The rationale in selecting threshold voltages can be governed by Equations (1), (2), and (3). However, this is inadequate to estimate suboptimality.…”

Section: Suboptimality Of V Th Assignmentmentioning

confidence: 99%

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Impact of range and precision in technology on cell-based design

Lee

Gupta

2012

Proceedings of the International Conference on Computer-Aided Design

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With the introduction of non-planar CMOS technologies in commercial designs, the effects of the range and precision allowed in a technology is an important. The limited range and precision (i.e. granularity) in a technology, and consequently, in a standard cell design, may result in significant penalties in the power and delay performance in a design. In this work, the impact of the range and precision is examined by providing a new framework for estimating the power suboptimality incurred by a design relative to a given library. Methods that predict the suboptimality well, both qualitatively and quantitatively, and the implications on standard cell library design are explored. While no other methods for estimating suboptimality are known, compared to a method derived from literature, our method provides a nearly 2x better estimate for v th assignment and 10x improvement for gate sizing.

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Section: Small Circuit Experimentsmentioning

confidence: 91%

Section: Ieee/acm International Conference On Computer-aided Design (mentioning

confidence: 99%

Section: Ieee/acm International Conference On Computer-aided Design (mentioning

confidence: 99%

“…The rationale in selecting threshold voltages can be governed by Equations (1), (2), and (3). However, this is inadequate to estimate suboptimality.…”

Section: Suboptimality Of V Th Assignmentmentioning

confidence: 99%

See 2 more Smart Citations

Impact of range and precision in technology on cell-based design

Lee

Gupta

2012

Proceedings of the International Conference on Computer-Aided Design

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“…However, all variants are generated for each new function, greatly enlarging the size of the library and thus the design space for the technology mapping. [5] and [4] aim at proposing low power libraries. In particular, [5] manually identifies the functions to be included into the library and, then, it applies a genetic algorithm to optimize the technology parameters, followed by hand-tuning.…”

Section: Related Workmentioning

confidence: 99%

A design methodology for the automatic sizing of standard-cell libraries

Pilato

Ferrandi

Pandini

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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Current EDA tools are often based on standard-cell libraries for the design of modern complex systems-on-chip. In general, there are opposite trends to compact and extend the standard cell libraries, and to move towards custom libraries, highly optimized for specific goals (e.g., area, timing or power consumption) or designs. We thus propose a design methodology for library sizing that combines decimation strategies and generation of cell variants. The proposed methodology is based on Simulated Annealing, also integrating heuristic principles to efficiently guide the exploration process. The approach has been validated on a set of common benchmarks for logic synthesis, demonstrating interesting results, specially when starting from a relative small initial library.

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Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

et al. 2023

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In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuit's performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuit's performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5%. The shortest library (7-track) resulted in 55% energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V.INDEX TERMS CMOS digital integrated circuit, energy efficiency, near-threshold voltage, P/N ratio optimization, standard cell height.

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Power efficient standard cell library design

Cited by 6 publications

References 3 publications

Impact of range and precision in technology on cell-based design

Impact of range and precision in technology on cell-based design

A design methodology for the automatic sizing of standard-cell libraries

Energy-Performance Optimization via P/N Ratio Sizing With Full Diffusion Layout Structure and Standard Cell Height Tuning in Near-Threshold Voltage Operation

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