Healthcare solutions through the introduction of wearable healthcare devices are benefitting from Internet of Things technology. Though these small form-factor wearable devices promise great benefits, guaranteeing long device operating lifetime is yet the biggest challenge due to high-energy consumption. In this paper, a reduced hardware architecture system-on-chip targeting digital block design was proposed higher energy efficiency. The design has been verified by synthesizing into FPGA and implemented in silicon based on Silterra 180nm process. Results show that the proposed design achieved reduction up to 24% of leakage power and 15% of dynamic power reduction over reference design. In addition, 24.3% of excessive area was reduced by using the proposed reduced hardware architecture technique.
This paper presents about the development of Software-as-a-Service tool for standard cell library characterization -ASCLIC. ASCLIC was created because many standard cell characterization software that exists are not easily accessible by public. Furthermore, it requires expensive paid license otherwise standard cell library characterization must be done manually. ASCLIC available as a web service that offers same function as another standard cell characterization. Simply upload netlist, model if available and configurations and the results will be emailed back to the user. Based on the results, the highest percentage changes for process technology of 130nm are 0.00172%, 1.92737% and 0.00198% of leakage power, internal power and timing respectively. In short, ASCLIC aims to give benefits to others especially educational institution for research purposes.
In recent decades, near-threshold voltage (NTV) design has become a well-known technique for improving the energy efficiency of digital integrated circuits. However, scaling down the operating voltage to the NTV raises two major challenges for robust operation: process variability and performance degradation. In this study, we propose a joint optimization technique for standard cell design to address the challenge of performance degradation in NTV design. The standard cell P/N ratio (PMOS width to NMOS width ratio) is being sized to maximize the performance with the constraint of a full diffusion (FD) layout structure, and the standard cell height is jointly optimized to further improve the circuit's performance or energy consumption. Increasing the standard cell height improves the circuit performance at the cost of higher energy consumption, whereas lowering the standard cell height sacrifices the circuit's performance for better energy saving. The results showed that implementing the taller library (14-track) in an AMBA high-speed bus (AHB) controller circuit can improve performance by up to 4.5%. The shortest library (7-track) resulted in 55% energy savings in the same circuit implementation. The test chip fabricated in 110-nm CMOS technology demonstrated successful operation of 8051 microcontroller down to 0.6V with the custom-designed 7-track library. The measurement results showed 4.3X energy saving compared to the operation at a supply voltage of 1.2V.INDEX TERMS CMOS digital integrated circuit, energy efficiency, near-threshold voltage, P/N ratio optimization, standard cell height.
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