Power Efficient Design of Multiplexer based Compressor using Adiabatic Logic

Singh, Richa; Sharma, Anjali; Singh, Rohit

doi:10.5120/14052-2217

Cited by 12 publications

(8 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The area minimisation and access time in addition to reduction of failure probabilities due to these variations should be taken care of for an optimal design using SRAM cell using FinFETs. The failure processes such as hot carrier injection, negative and positive bias temperature instability, and temperature-dependent dielectric breakdown can have great impact on the working of an individual transistor and hence also a threat to the entire circuit [9]. Thus, the robust circuit design is required for the successful working of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Low‐power and high‐speed 13T SRAM cell using FinFETs

Saxena

Mehra

2017

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

show abstract

Section: Introductionmentioning

confidence: 99%

Low‐power and high‐speed 13T SRAM cell using FinFETs

Saxena

Mehra

2017

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…It is due to limited power supply through battery. So circuit should consume less power [4].In current scenario smart portable electronics with high resolution CMOS image sensors become very popular. To achieve high resolution, low cost CMOS image sensor in a thin and compact smart electronic devices pixel dimension of the CIS are getting smaller [5].…”

Section: Introductionmentioning

confidence: 99%

Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology

Yadav¹,

Mehra²,

Sehgal³

2016

IOSR

View full text Add to dashboard Cite

An integrating type ADC is the most commonly used column level ADC for its simple architecture and small surface area. 12-bit Dual slope ADC is developed which has less complexity in design. This architecture has basic advantage that it eliminates the dependence of the conversion on the linearity and accuracy of the slope. The main block of this circuit is opamp. Two stage opamp is developed which has gain of 78dB. Dual slope integrator is designed which has one resistance in feed forward path and one feedback capacitance with opamp circuit. This dual slope column level ADC minimizes the conversion time. CMOS process is used because it provides high integration capabilities. This column level dual slope ADC is implemented using 180nm technology.

show abstract

“…The betray lifetime of such devices is nice concern. When mobile phone is operated in standby mode, bound programs of mobile phone are turned off throughout active mode but this does not stop the battery from obtaining depleted [1] [2]. This is because circuits which are de-activated by turning off bound programs still have discharge currents flowing through them.…”

Section: Introductionmentioning

confidence: 99%

Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime

Bhargava¹,

Sharma²,

Akashe³

2013

IJCA

View full text Add to dashboard Cite

As transistor sizes scale down and levels of integration increase, leakage power has become a vital downside in modern low-power VLSI technology. This is often very true for ultra-low-voltage (ULV) circuits, wherever high levels of leakage force designers to selected relatively high threshold voltages, which limits performance. In this paper, we design different design approach of master slave D flip-flop with stacking power gating leakage reduction technique. Here these techniques essentially increase the effective resistance of leakage paths by adding sleep transistors between logic stacks and power supply rails. Power gating technique also provides many of the property from transistor stacking technique. The proposed approach saves maximum amount of the Leakage power without degrading the performance of the circuit. In this work we analyses the leakage power of three different types of CMOS design style such as pass transistor logic (PTL), transmission gates and gate diffusion input (GDI) design. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameters.

show abstract

Power Efficient Design of Multiplexer based Compressor using Adiabatic Logic

Cited by 12 publications

References 12 publications

Low‐power and high‐speed 13T SRAM cell using FinFETs

Low‐power and high‐speed 13T SRAM cell using FinFETs

Optimized Design of Column Level ADC for CMOS Imager using 180 nm Technology

Reduction of Leakage Power using Stacking Power Gating Technique in Different CMOS Design Style at 45Nanometer Regime

Contact Info

Product

Resources

About