Power efficient charge pump in deep submicron standard cmos technology

Pelliconi, Roberto; Iezzi, D.; Baroni, A.; Pasotti, M.; Rolandi, P.L.

doi:10.1109/jssc.2003.811991

Cited by 225 publications

(85 citation statements)

References 5 publications

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“…5b. These dual-branch structures were introduced to lower ripples in the CTS design (Kleveland, 2002;New et al, 2012) and later evolved into latch-based designs (Nakagome et al, 1991;Gariboldi and Pulvirenti, 1994;1996;Favrat et al, 1998;Pelliconi et al, 2003;Ker et al, 2006;Che et al, 2009;Chen et al, 2010;Ulaganathan et al, 2012;Peng et al, 2014;Kim et al, 2015) which are currently gaining popularity. These structures have V OUT similar to Equation 1 but with reduced charge transfer intervals of T/2 (Palumbo and Pappalardo, 2010), circuit minimization with smaller C PUMP values and half the ripple, V R compared to single branch CPs where V R is expressed as V R = I OUT T/[2(C OUT +C PUMP )] (Pan and Samaddar, 2010) assuming C OUT >> C PUMP .…”

Section: Dual-branch Charge Pumpmentioning

confidence: 99%

“…Hence, the CPs either uses switches or capacitors efficiently, but not simultaneously superior in both asymptotes (Seeman and Sanders, 2008). Recently, Bazzini et al (2012) proposes an all PMOS Double Ladder CP which lowers output resistance, R OUT(OPT) Pelliconi et al (2003) design with the i-stage pumping capacitor, C PUMP(i) = (N+1-i)/(N(N+1)C TOT (Bazzini et al, 2012) chosen to minimize R OUT (Makowski and Maksimovic, 1995). While this enhanced structure has a high VCE at 93%, it still suffers a low PCE at 52%.…”

Section: Miscellaneous Charge Pumpsmentioning

confidence: 99%

See 1 more Smart Citation

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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This paper reviews CMOS based charge pump topologies used within autonomous embedded micro-systems. These charge pump structures have evolved from its simplistic diode-tied, single-branches with major threshold drops to exponential type, dual-branches with sophisticated gate and substrate control for lower voltage operation. Published charge pumps are grouped based on architecture, operation principles and pump optimization techniques with their pros and cons compared and results contrasted. The various charge pump topologies and schemes used are considered based on pumping efficiency, power efficiency, charge transferability, circuit complexity, pumping capacitors, form factor and minimum supply voltages with an optimum load. This article concludes with an overview of suitable techniques and recommendations that will aid a designer in selecting the most suitable charge pump topology especially for low ambient micro energy harvesting applications.

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Section: Dual-branch Charge Pumpmentioning

confidence: 99%

Section: Miscellaneous Charge Pumpsmentioning

confidence: 99%

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Mi¹,

Islam

Sampe

et al. 2016

American Journal of Applied Sciences

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show abstract

“…The efficiencies for solutions with on-chip inductors and pump capacitors are highly dependent on the load conditions and voltage increase ratio. For a converter with an on-chip inductor an efficiency of 28% has been reported [21], while the capacitive pump has achieved 65% [23]. The large value of the target capacitance of the piezoelectric transducer (nF-range) further hampers the efficiency of an on-chip solution, as the achievable capacitance and inductance values are low.…”

Section: Pulse Generation Strategymentioning

confidence: 99%

Ultra-low power transmit/receive ASIC for battery operated ultrasound measurement systems

Johansson

Gustafsson

Delsing

2006

Sensors and Actuators A: Physical

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AbsractThis paper describes the design of the complete transmit and receive electronics circuitry for a piezoelectric transducer in one single ASIC. The chip will be one building block in a thumb size battery operated ultrasound measurement system. The main design target has been to achieve extremely low power consumption while keeping the number of external components minimal.To overcome the dynamic range limitations imposed by a battery supply an on-chip boost converter uses one external inductor to generate up to 40 V for excitation of the transducer. The transducer itself is used as a storage capacitor, whereafter it is rapidly discharged to generate an ultrasound pulse. An on-chip amplifier with intermittent operation is controlled by a state machine and used to amplify incoming echoes. The chip has been fabricated in a 0.8 m high voltage CMOS process, with a total chip area of 12 mm 2 . Measurements verify the design approach. The power consumption for the system reaches within a factor of 2 of the power needed to charge the capacitance of the piezoelectric transducer from a fixed voltage source. The results show the possibility to achieve extremely low power consumption in a battery operated pulse-echo ultrasound measurement system.

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“…The simple structure of it makes charge pump popular in applications such as read/write operation of EEPROM and MEMS MIC, which have relatively low load current with moderate ripple requirements [1][2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

“…Thus, for higher output voltage, more stages than the theoretically expected is required. Several advanced designs with focuses on CMOS reliability, higher load current driving ability, and small chip area [3][4][5] have been published. Nevertheless, those designs are not suitable for the applications where low input voltage is given and when transistors have relatively high threshold voltages.…”

Section: Introductionmentioning

confidence: 99%

Improved Charge Pump with Reduced Reverse Current

Gwak¹,

Lee²,

Ryu³

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A highly efficient charge pump that minimizes the reverse charge sharing current (in short, reverse current) is proposed. The charge pump employs auxiliary capacitors and diode-connected MOSFET along with an early clock to drive the charge transfer switches; this new method provides better isolation between stages. As a result, the amount of reverse current is reduced greatly and the clock driver can be designed with reduced transition slope. As a proof of the concept, a 1.1V-to-9.8 V charge pump was designed in a 0.35 µm 18 V CMOS technology. The proposed architecture shows 1.6 V ~ 3.5 V higher output voltage compared with the previously reported architecture.

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Power efficient charge pump in deep submicron standard cmos technology

Cited by 225 publications

References 5 publications

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Review of Charge Pump Topologies for Micro Energy Harvesting Systems

Ultra-low power transmit/receive ASIC for battery operated ultrasound measurement systems

Improved Charge Pump with Reduced Reverse Current

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