Power delivery validation methodology and analysis for network processors

Suryakumar, M.; Cui, Weimin; Parmar, P.; Carlson, C.; Fishbein, Bruce J.; Sheth, U.; Morgan, J.

doi:10.1109/ectc.2004.1319398

Cited by 9 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…From Figure 7 one can observe that the lite package has -3OuOhm of higher resistance than the heavy package at the hotspot nodes and this primarily due to reduction in VSS copper in the lite package design. [4]. The die stimulus representative of this was modeled as a Gpoly network and attached to the power and ground nodes of the distributed power delivery network.…”

mentioning

confidence: 99%

Design and Performance Analysis of Dual Die Pentium® 4 Package

Sarangi

Suryakumar

2006

2006 IEEE Electrical Performane of Electronic Packaging

View full text Add to dashboard Cite

The continued growth of power consumption has presented numerous packaging challenges for high performance processors. Even though voltage is a strong knob to reduce power, reducing voltage also reduces the maximum operating frequency [1]. Integrating more cores into the processor would result in better performance and power efficiency but this requires more memory accesses, driving a need for larger cache and high speed signaling, increasing package size and layer count. This paper discusses the design strategy for power delivery and compares performance of the dual die packages through measurements.

show abstract

mentioning

confidence: 99%

Design and Performance Analysis of Dual Die Pentium® 4 Package

Sarangi

Suryakumar

2006

2006 IEEE Electrical Performane of Electronic Packaging

View full text Add to dashboard Cite

show abstract

“…Each droop is related to the local decoupling capacitor and inductor networks. [5] Low frequency noise was measured at the droop around the microsecond range. Figure 15 and Figure 16 show the major factors that affect mid-frequency noise and low-frequency noise, respectively.…”

Section: Results Of Analysesmentioning

confidence: 99%

Electrical Design Optimization and Characterization in Cell Broadband Engine Package

Goto

Hosomi

Harvey³

et al.

56th Electronic Components and Technology Conference 2006

View full text Add to dashboard Cite

Cell Broadband Engine is a microprocessor that has very high processing performance and very high speed I/O to communicate with other devices such as system LSI and memory chips. Design optimization with statistical analysis was carried out.DOE matrix was made with dimension of signal traces and dielectric constant of the insulator in the package substrate. After major factors were detected, random sampling was done to make sure that the distribution of characteristic impedance of signal traces is within the specification. Passive characterization was carried out with test vehicle. Insertion loss and characteristic impedance is dependent on both temperature and water absorption. These environmental factors need to be taken into account when the design rule is determined. After design rule is fixed, circuit simulation for whole signal channel was carried out with considering impedance tolerance in both the package and the printed circuit board.DOE matrix was made and analyzed to determine the major factors on mid-frequency and low-frequency noise in power distribution. Inductance of package substrate and decoupling capacitor are the major effect on the midfrequency noise, and capacitance of on-module and on-PCB affect low frequency noise. The effect of on-chip parameters was also evaluated. Several types of capacitors were characterized to measure their parasitic parameters. 1.. IntroductionCell Broadband Engine is a multi-core microprocessor based on the state-of-the-art architecture. Details of the chip architecture and internal performance are described in otherFrom a packaging standpoint, Cell Broadband Engine is very challenging for both signal and power integrity. Cell Broadband Engine needs to communicate with other system LSIs and memory chips for input and output of processed data. The bandwidth of chip-to-chip and memory interface is quite large compared to other devices. It needs to increase both the I/O frequency and the number of signal pins. [4] Signal density in the package substrate needs to be increased. It will cause more coupling noise, and degrade both timing and voltage margin. Since I/O frequency is so high, noise issue is very critical to assure the operation of high performance microprocessor.Noise issue is also critical for power distribution design. Because of the high performance of Cell Broadband Engine, operating frequency of processing units is also increased. It means that simultaneous switching noise due to current switching in the processor core will be increased. However, operating voltage tends to be lowered to decrease power consumption. Package designers have to manage these two opposed issues.As stated above, the allowable margin to assure the performance is being decreased. For instance, characteristic impedance of high speed signals needs to be tightly controlled to avoid the loss caused by the reflection at the boundary of package and printed circuit board (PCB). Tight control of dimensions of signal trace is required, but too tight control will affect manufacturing yield a...

show abstract

IC-Package-System Integration Design

Shi

Shang

et al. 2013

Advanced Flip Chip Packaging

View full text Add to dashboard Cite

Power delivery validation methodology and analysis for network processors

Cited by 9 publications

References 0 publications

Design and Performance Analysis of Dual Die Pentium® 4 Package

Design and Performance Analysis of Dual Die Pentium® 4 Package

Electrical Design Optimization and Characterization in Cell Broadband Engine Package

IC-Package-System Integration Design

Contact Info

Product

Resources

About