Electrical Design Optimization and Characterization in Cell Broadband Engine Package

Abstract

Cell Broadband Engine is a microprocessor that has very high processing performance and very high speed I/O to communicate with other devices such as system LSI and memory chips. Design optimization with statistical analysis was carried out.DOE matrix was made with dimension of signal traces and dielectric constant of the insulator in the package substrate. After major factors were detected, random sampling was done to make sure that the distribution of characteristic impedance of signal traces is within the specification. Passive characterization was carried out with test vehicle. Insertion loss and characteristic impedance is dependent on both temperature and water absorption. These environmental factors need to be taken into account when the design rule is determined. After design rule is fixed, circuit simulation for whole signal channel was carried out with considering impedance tolerance in both the package and the printed circuit board.DOE matrix was made and analyzed to determine the major factors on mid-frequency and low-frequency noise in power distribution. Inductance of package substrate and decoupling capacitor are the major effect on the midfrequency noise, and capacitance of on-module and on-PCB affect low frequency noise. The effect of on-chip parameters was also evaluated. Several types of capacitors were characterized to measure their parasitic parameters. 1.. IntroductionCell Broadband Engine is a multi-core microprocessor based on the state-of-the-art architecture. Details of the chip architecture and internal performance are described in otherFrom a packaging standpoint, Cell Broadband Engine is very challenging for both signal and power integrity. Cell Broadband Engine needs to communicate with other system LSIs and memory chips for input and output of processed data. The bandwidth of chip-to-chip and memory interface is quite large compared to other devices. It needs to increase both the I/O frequency and the number of signal pins. [4] Signal density in the package substrate needs to be increased. It will cause more coupling noise, and degrade both timing and voltage margin. Since I/O frequency is so high, noise issue is very critical to assure the operation of high performance microprocessor.Noise issue is also critical for power distribution design. Because of the high performance of Cell Broadband Engine, operating frequency of processing units is also increased. It means that simultaneous switching noise due to current switching in the processor core will be increased. However, operating voltage tends to be lowered to decrease power consumption. Package designers have to manage these two opposed issues.As stated above, the allowable margin to assure the performance is being decreased. For instance, characteristic impedance of high speed signals needs to be tightly controlled to avoid the loss caused by the reflection at the boundary of package and printed circuit board (PCB). Tight control of dimensions of signal trace is required, but too tight control will affect manufacturing yield a...

Chip/Package Design and Technology Trade-offs in the 65nm Cell Broadband Engine

“…The details of this statistical approach can be found in a previous paper [1]. Figure 5 outlines the factors and tolerances in the study.…”

“…High speed signals were routed on the top build-up layers in the package and then down thru via stacks to the corresponding BGA balls. This was done successfully in the 90nm package design which has been in high volume production for some time [1].…”

“…In the laminate construction for the original 90nm Cell processor, the C4 footprint was devised to meet the minimum PTH pitch available from the laminate suppliers at reasonable cost [1]. This provided a well optimized current loop with minimal inductance from the chip, thru the substrate, to the decoupling capacitors on the backside.…”

“…The package design and construction were driven by principal chip performance requirements for the efficient power and signal distribution at optimal cost. The optimization of these design factors in the 90nm CELL BE packaging was described previously [1]. CELL [3,4].…”

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Technology migration of the Cell Broadband Engine.TM (BE) Microprocessor to 65nm chip technology precipitated a redesign of the original IC packaging [1,2]. While many of the design changes were necessitated by the chip technology migration, other modifications were implemented to enhance the robustness and overall manufacturability of the product.

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