Design and Performance Analysis of Dual Die Pentium® 4 Package

Abstract

The continued growth of power consumption has presented numerous packaging challenges for high performance processors. Even though voltage is a strong knob to reduce power, reducing voltage also reduces the maximum operating frequency [1]. Integrating more cores into the processor would result in better performance and power efficiency but this requires more memory accesses, driving a need for larger cache and high speed signaling, increasing package size and layer count. This paper discusses the design strategy for power delivery and compares performance of the dual die packages through measurements.