A microarchitecture-based framework for pre- and post-silicon power delivery analysis

Ketkar, Mahesh; Chiprout, Eli

doi:10.1145/1669112.1669136

Cited by 26 publications

(10 citation statements)

References 11 publications

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“…Specialized micro-benchmarks known as di/dt stressmarks are used to generate worst-case workload-induced voltage droops [7][8] [9] [10]. We use stressmarks as described in [10] to determine the voltage guardband necessary during normal operation and when FP throttling is enabled.…”

Section: A Di/dt Stressmarksmentioning

confidence: 99%

“…These droops may be singleevent or resonating droops, as illustrated in Figure 1. High di/dt stress occurs when a region of high-power instructions is followed by a region of low-power instructions [5] [7][8] [9] [10]; if these instruction sequences repeat periodically, it may cause resonating droops. In general, resonant droops are more likely to induce failures than singleevent droops because they are larger and repeat periodically.…”

Section: Introductionmentioning

confidence: 99%

“…The worst-case guardband of a system typically is determined using di/dt stressmarks, which are special programs designed to induce large di/dt voltage droops [5] [7][8] [9] [10]. These stressmarks contain operations that utilize the high-power-consuming functional units/pipelines.…”

Section: Introductionmentioning

confidence: 99%

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Performance boosting under reliability and power constraints

John¹,

Paul²,

Manne³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We then examine the impact of FP throttling and guardband reduction on the SPEC CPU2006 benchmarks and show that some benchmarks benefit from the frequency improvements with FP throttling while others suffer due to reduced FP throughput.Finally, we present two techniques to determine dynamically when to trade FP throughput for reduced voltage margin and increased frequency, and show performance improvements of up to 15% for CINT2006 benchmarks and up to 8% for CFP2006 benchmarks. Our studies are done on hardware in which FP units generate the worst-case voltage droop. The technique can be modified for architectures in which other units cause the worst droop.

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Section: A Di/dt Stressmarksmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance boosting under reliability and power constraints

John¹,

Paul²,

Manne³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Ketkar and Chiprout proposed a di/dt stressmark generation methodology using integer linear program (ILP) scheduling [7]. They identified di/dt stressmark generation as an instruction scheduling and resource allocation problem.…”

Section: Related Workmentioning

confidence: 99%

Automated di/dt stressmark generation for microprocessor power delivery networks

Kim

John

2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-In this paper, we propose a method for automated di/dt stressmark generation to test maximum voltage droop in a microprocessor power delivery network. The di/dt stressmark is an instruction sequence which draws periodic high and low current pulses that maximize voltage fluctuations including voltage droops. In order to automate di/dt stressmark generation, we devise a code generator with the ability to control instruction sequencing, register assignments, and dependencies. Our framework uses a Genetic Algorithm in scheduling and optimizing candidate instruction sequences to create a maximum voltage droop. The results show that our automatically generated di/dt stressmarks achieved more than 40% average increase in voltage droop compared to hand-coded di/dt stressmarks and typical benchmarks in experiments covering three microprocessor architectures and five power delivery network (PDN) models. Additionally, our method considers all the units in a microprocessor, as opposed to a previous ILP scheduling method that handles only execution units.Keywords -voltage droop; microprocessor power delivery network; di/dt stressmark; system-level power-aware design

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“…Smith et al [4] developed a method to systematically characterize the PDN noise. Ketkar et al [14] studied micro-architecture based framework for PDN analysis. Chiprout [15] discussed pre-silicon stimulus and post-silicon activity generation to excite the worst-case voltage drop.…”

Section: Introductionmentioning

confidence: 99%

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

Zhang¹,

Liu

et al. 2014

Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop

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Abstract-We propose a prediction of the worst-case noise area of the supply voltage on the power distribution network (PDN). Previous works focus on the worst-peak droop to sign off PDN. In this work, we (1) study the behavior of circuit delay over the worst-area noise (2) study the worst-case noise area of a lumped PDN model (3) develop an algorithm to generate the worst-case current for general PDN cases (4) predict the longest delay of a datapath due to power integrity. Experimental results show that the worst-area noise induces additional delay than that of the worst-peak noise.

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A microarchitecture-based framework for pre- and post-silicon power delivery analysis

Cited by 26 publications

References 11 publications

Performance boosting under reliability and power constraints

Performance boosting under reliability and power constraints

Automated di/dt stressmark generation for microprocessor power delivery networks

Worst-Case Noise Area Prediction of On-Chip Power Distribution Network

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