Automated di/dt stressmark generation for microprocessor power delivery networks

Kim, Ki Wook; John, John

doi:10.1109/islped.2011.5993645

Cited by 30 publications

(13 citation statements)

References 13 publications

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“…One special case of inductive noise happens when the load current fluctuates at the resonance frequency of the PDN, exciting its peak impedance. Generally speaking, resonance is the cause for worst-case voltage noise in modern processors [9].…”

Section: Introductionmentioning

confidence: 99%

Characterizing and evaluating voltage noise in multi-core near-threshold processors

Zhang¹,

Tong²,

Kanev³

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Lowering the supply voltage to improve energy efficiency leads to higher load current and elevated supply sensitivity. In this paper, we provide the first quantitative analysis of voltage noise in multi-core near-threshold processors in a future 10nm technology across SPEC CPU2006 benchmarks. Our results reveal larger guardband requirement and significant energy efficiency loss due to power delivery nonidealities at near threshold, and highlight the importance of accurate voltage noise characterization for design exploration of energy-centric computing systems using near-threshold cores.

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Section: Introductionmentioning

confidence: 99%

Characterizing and evaluating voltage noise in multi-core near-threshold processors

Zhang¹,

Tong²,

Kanev³

et al. 2013

International Symposium on Low Power Electronics and Design (ISLPED)

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“…Experimental results are measured on a POWER7-based 8-core/32-thread system [42] in order to validate the efficacy of MicroProbe. This is quite different from prior work [13,20,33,34,39,40], where 'black-box' automatic test case generators are focused on stressing or validating only a single metric: e.g. IPC, power or some utilizationbased index of performance or power.…”

Section: Introductionmentioning

confidence: 80%

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Bertran

Buyuktosunoglu

Gupta

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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Microprocessor-based systems today are composed of multi-core, multi-threaded processors with complex cache hierarchies and gigabytes of main memory. Accurate characterization of such a system, through predictive pre-silicon modeling and/or diagnostic postsilicon measurement based analysis are increasingly cumbersome and error prone. This is especially true of energy-related characterization studies. In this paper, we take the position that automated micro-benchmarks generated with particular objectives in mind hold the key to obtaining accurate energy-related characterization. As such, we first present a flexible micro-benchmark generation framework (MicroProbe) that is used to probe complex multi-core/multithreaded systems with a variety and range of energy-related queries in mind. We then present experimental results centered around an IBM POWER7 CMP/SMT system to demonstrate how the systematically generated micro-benchmarks can be used to answer three specific queries: (a) How to project application-specific (and if needed, phase-specific) power consumption with component-wise breakdowns? (b) How to measure energy-per-instruction (EPI) values for the target machine? (c) How to bound the worst-case (maximum) power consumption in order to determine safe, but practical (i.e. affordable) packaging or cooling solutions? The solution approaches to the above problems are all new. Hardware measurement based analysis shows superior power projection accuracy (with error margins of less than 2.3% across SPEC CPU2006) as well as maxpower stressing capability (with 10.7% increase in processor power over the very worst-case power seen during the execution of SPEC CPU2006 applications).

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“…Similarly, in Biswas et al [2005], we see different AVF values for the considered benchmark applications. A paper that deals with the impact of ported SW on reliability metrics is Kim et al [2011]. This work employs a genetic algorithm to maximize the inductance impact (di/dt) on the power delivery network (PDN).…”

Section: Violationsmentioning

confidence: 99%

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Rodopoulos¹,

Psychou

Sabry

et al. 2015

ACM Comput. Surv.

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Technology downscaling is expected to amplify a variety of reliability concerns in future digital systems. A good understanding of reliability threats is crucial for the creation of efficient mitigation techniques. This survey performs a systematic classification of the state of the art on the analysis and modeling of such threats, which are caused by physical mechanisms to digital systems. The purpose of this article is to provide a classification tool that can aid with the navigation across the entire landscape of reliability analysis and modeling. A classification framework is constructed in a top-down fashion from complementary categories, each one addressing an approach on reliability analysis and modeling. In comparison to other classifications, the proposed methodology approaches the target research domain in a complete way, without suppressing hybrid works that fall under multiple categories. To substantiate the usability of the classification framework, representative works from the state of the art are mapped to each appropriate category and are briefly analyzed. Thus, research trends and opportunities for novel approaches can be identified.

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Automated di/dt stressmark generation for microprocessor power delivery networks

Cited by 30 publications

References 13 publications

Characterizing and evaluating voltage noise in multi-core near-threshold processors

Characterizing and evaluating voltage noise in multi-core near-threshold processors

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

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