Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Rodopoulos, Dimitrios; Psychou, Georgia; Sabry, Mohamed M.; Catthoor, Francky; Papanikolaou, Apostolos; Soudris, Dimitrios; Noll, Tobias G.; Atienza, David

doi:10.1145/2678276

Cited by 8 publications

(15 citation statements)

References 75 publications

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“…The classification is not restricted with respect to the type of the fault occurring on the systems, i.e. it includes techniques for both parametric and functional errors [40]. The classification does not focus on separating the techniques to different abstraction levels of the digital system design, as each class can be further instantiated to the appropriate abstraction levels depending on the requirements of the design.…”

Section: Target Domain and Problem Formulationmentioning

confidence: 99%

Binary Tree Classification of Rigid Error Detection and Correction Techniques

et al. 2020

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Due to technology scaling and harsh environments, a wide range of fault-tolerant techniques exists to deal with the error occurrences. Selecting a fault-tolerant technique is not trivial, whereas more than the necessary overhead is usually inserted during the system design. To avoid over-designing, it is necessary to have an in-depth understanding of the available design options. However, an exhaustive listing is neither possible to create nor efficient to use due to its prohibitive size. In this work, we present a top-down binary tree classification for error detection and correction techniques. At each split, the design space is clearly divided into two complementary parts using one single attribute, compared with existing classifications that use splits with multiple attributes. A leaf inherits all the attributes of its ancestors from the root to the leaf. A technique is decomposed into primitive components, each one belonging to a different leaf. The single attribute splits can be used to efficiently compare the techniques and to prune the incompatible parts of the design space during the design of a technique. This essential single attribute division of the design space is required for the improvement of the techniques and for novel contributions to the fault-tolerance domain.

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Section: Target Domain and Problem Formulationmentioning

confidence: 99%

Binary Tree Classification of Rigid Error Detection and Correction Techniques

et al. 2020

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“…In addition, there are other techniques for analyzing and modeling which are beyond the scope of this dissertation [130] such as injecting (black-box controllability), detecting (black-box observability), and modeling reliability metric for a digital systems.…”

Section: Electro-migration (Em)mentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers-The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workloa...

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“…Traditionally, causal models are represented as a relationship between fault, error and failure [22]. We define causal model as the impact of communication related phenomena on process execution.…”

Section: Causal Modelmentioning

confidence: 99%

Inter-Process Correlation Model based Hybrid Framework for Fault Diagnosis in Wireless Sensor Networks

2019

KSII TIIS

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Soft faults are inherent in wireless sensor networks (WSNs) due to external and internal errors. The failure of processes in a protocol stack are caused by errors on various layers. In this work, impact of errors and channel misbehavior on process execution is investigated to provide an error classification mechanism. Considering implementation of WSN protocol stack, inter-process correlations of stacked and peer layer processes are modeled. The proposed model is realized through local and global decision trees for fault diagnosis. A hybrid framework is proposed to implement local decision tree on sensor nodes and global decision tree on diagnostic cluster head. Local decision tree is employed to diagnose critical failures due to errors in stacked processes at node level. Global decision tree, diagnoses critical failures due to errors in peer layer processes at network level. The proposed model has been analyzed using fault tree analysis. The framework implementation has been done in Castalia. Simulation results validate the inter-process correlation model-based fault diagnosis. The hybrid framework distributes processing load on sensor nodes and diagnostic cluster head in a decentralized way, reducing communication overhead.

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Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Cited by 8 publications

References 75 publications

Binary Tree Classification of Rigid Error Detection and Correction Techniques

Binary Tree Classification of Rigid Error Detection and Correction Techniques

Reliability Modeling and Mitigation for Embedded Memories

Inter-Process Correlation Model based Hybrid Framework for Fault Diagnosis in Wireless Sensor Networks

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