Power considerations in the design of the Alpha 21264 microprocessor

Abstract

Power dissipation is rapidly becoming a limiting factor in high performance microprocessor design due to ever increasing device counts and clock rates. The 21264 is a third generation Alpha microprocessor implementation, containing 15.2 million transistors and operating at 600 MHz. This paper describes some of the techniques the Alpha design team utilized to help manage power dissipation. In addition, the electrical design of the power, ground, and clock networks is presented.

Dynamically exploiting narrow width operands to improve processor power and performance

“…In some highend CPUs much of the power is spent on clock distribution and control logic, and thus the integer unit represents only about 10% of the power dissipation [19]. In such a processor, our optimizations will lead to 5-6% power reductions on average.…”

Scaling and Packing on a Chip Multiprocessor

“…Many researchers reduce power with novel microarchitectures [29,6,13,21]. A compiler can generate power-aware code [19,44,45].…”

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

“…The drawback in such designs is that a significant amount of chip area (in the form of decaps) is devoted to the coverage of those infrequent corner cases. For example, the Alpha 21264 reported that roughly 15 to 20% of the die area is occupied by decaps [8] and the trend is going up. Also note that, these decaps will contribute a considerable amount of leakage power in future deep submicron processors.…”

“…In contrast, the entries in the di/dt controller queue are pre-wired for each module at design time to simplify the logic for driving clock-gating signals directly to the modules. 8 However, 7 Please note that in a real implementation, the sliding window will have an upper limit in terms of how many modules weights can be computed in a given cycle. 8 Since the queue entries are pre-wired to the clock gating output, it is possible to apply certain heuristics to the order of modules in the queue with asymmetric weights, in order to permit the maximum possible transition at a given time.…”