Proceedings Fifth International Symposium on High-Performance Computer Architecture 1999
DOI: 10.1109/hpca.1999.744314
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Dynamically exploiting narrow width operands to improve processor power and performance

Abstract: In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily

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Cited by 223 publications
(200 citation statements)
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“…Results shown in Figure 1 suggest that significantly better use of a register file is possible if narrow width results can be packed within a single 64-bit physical register. This observation has motivated this work, as well as the works of [27,31,24] …”
Section: Motivationsmentioning
confidence: 99%
See 1 more Smart Citation
“…Results shown in Figure 1 suggest that significantly better use of a register file is possible if narrow width results can be packed within a single 64-bit physical register. This observation has motivated this work, as well as the works of [27,31,24] …”
Section: Motivationsmentioning
confidence: 99%
“…It has been well documented in the recent literature that many operand and result values in a datapath have narrow width [27,31,24]. In this section, we analyze the data width characteristics of the SPEC 2000 benchmarks that were used in this work.…”
Section: Motivationsmentioning
confidence: 99%
“…In this paper, we do not focus on the energy savings due to zero byte encoding in other datapath components such as caches or function units, since they have been studied elsewhere [2,12].…”
Section: Sources Of Energy Dissipationmentioning
confidence: 99%
“…In [12], the same fact is used to reduce energy dissipations within the primary data and instruction caches for SPECint95 and other integer-dominated benchmarks. In [2], the presence of leading zero bytes in a result produced by integer function units are exploited. Energy savings possible within the explicit and implicit storage components of the datapath and floating-point dominated benchmarks are not considered in [2].…”
Section: Introductionmentioning
confidence: 99%
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