Power-balanced self checking circuits for cryptographic chips

Murphy, Julian P.; Bystrov, A.; Yakovlev, Alex

doi:10.1109/iolts.2005.56

Cited by 2 publications

(1 citation statement)

References 21 publications

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“…Techniques based on balancing power fluctuation include new CMOS logic gates [31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46], which go through a full charge/discharge cycle for each data processed. Asynchronous circuits, especially dual-rail encoded logic, have been well studied for anti-DPA because of the fixed switching activities during each DATA-Spacer cycle [47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65]. Other power balancing methods include modifying the algorithm execution [66][67][68][69], compensating current at the power supply node [70][71][72][73], and using subthreshold operation [74].…”

Section: Power-based Attacksmentioning

confidence: 99%

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Nair

Smith

2015

JLPEA

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As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electromagnetic interference (EMI). This paper develops the Delay-Insensitive Ternary Logic (DITL) asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB) and NULL Convention Logic (NCL) on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

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