Power-Aware Scheduling for Parallel Security Processors with Analytical Models

Abstract

Abstract. Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS), power gating (PG), and multipledomain partitioning are regarded as effective schemes to reduce dynamic and static power. In this paper, we investigate the problem of power-aware scheduling tasks running on a scalable encryption processor, which is equipped with heterogeneous distributed SOC designs and needs the effective integration of the elements of DVS, PG, and the scheduling for correlations of multiple domain resources. We propose a novel heuristic that integrates the utilization of DVS and PG and increases the total energy-saving. Furthermore, we propose an analytic model approach to make an estimate about its performance and energy requirements between different components in systems. These proposed techniques are essential and needed to perform DVS and PG on multiple domain resources which are of correlations. Experiments are done in the prototypical environments for our security processors and the results show that significant energy reductions can be achieved by incorporating our algorithms. 12

Low-power techniques for network security processors

“…In this section, we propose a real-time variablevoltage scheduling algorithm that scales the operating voltages of crypto modules of the network security processor dynamically by scheduling descriptors and evaluate the proposed approach in the end of this section. A more generic scheduling algorithm has been proposed in [4]. We assume that the descriptor-based network security processor contains several major crypto modules (CMs) which are capable of K-level supply voltages and power-gating (PG) mode.…”

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

“…As the application software is associated with early decisions of design, power optimization in the software layer will also give the opportunity for design option explorations. Early work in power optimizations from compiler viewpoints include reducing power consumption via software arrangements at instruction-level to reduce power consumption [2][3][4], compiler supports for instruction utilization analysis for leakage power reduction [2], software re-arrangements to utilize the value locality of registers [3], the scheduling of VLIW instructions to reduce the power consumption on the instruction bus [4], power optimizations with Sink-NHoist schemes [5], and energy aware scheduling for parallel security processors [6].…”