Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

Novo, David; Fasthuber, Robert; Raghavan, Praveen; Bourdoux, André; Li, M.; Perre, Liesbet Van der; Catthoor, Francky

doi:10.1109/sips.2009.5336241

Cited by 2 publications

(1 citation statement)

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“…Here, a finite impulse response (FIR) filter is used at the end of decimation chain to compensate for the droop in the signal band. Later, when Σ ADCs were developed for wireless applications, this architecture has been modified to optimize for area and power [9], [10], [11], [12], [13]. Several techniques borrowed from the digital signal processor (DSP) architectures have been borrowed to optimized the custom designed decimation filters.…”

Section: Introductionmentioning

confidence: 99%

Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs

Koppula

Balagopal

Saxena

2011

2011 IEEE International SOC Conference

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Abstract-A design methodology for synthesizing poweroptimized decimation filters for wideband Delta Sigma ( Σ ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuoustime Σ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12 mm 2 and consumes 8 mW power from the 1.1V supply.

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