Power and Area Efficient Squarer Design

Cho, Kyung-Ju; Kim, Yong-Eun; Chung, Jin-Gyun

doi:10.1109/acssc.2006.355055

Cited by 8 publications

(7 citation statements)

References 8 publications

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“…The Booth-folding technique (BFT) [3] has been shown to reduce 50% of the partial products, compared to a simple folding structure [2]. To reduce area overhead, the truncated fixed-width squarers with errorcompensation circuits for simple folding [4]- [5] and BFT [6] techniques are presented. The merged partial products squarer with an error-compensation circuit presented in [4] has proved a highly efficient design with regard to power usage and area efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…Squaring operations can be executed using a fixed-width multiplier; however, this tends to results in redundant circuitry when dealing with very-large-scale integration (VLSI) designs. Therefore, many squarers employ symmetry to reduce partial products [2]- [3] as well as error-compensation circuits to alleviate the effects of truncation errors associated with fixedwidth squarers [4]- [5]. The Booth-folding technique (BFT) [3] has been shown to reduce 50% of the partial products, compared to a simple folding structure [2].…”

Section: Introductionmentioning

confidence: 99%

“…To reduce area overhead, the truncated fixed-width squarers with errorcompensation circuits for simple folding [4]- [5] and BFT [6] techniques are presented. The merged partial products squarer with an error-compensation circuit presented in [4] has proved a highly efficient design with regard to power usage and area efficiency. Linear compensation was proposed with the aim of improving accuracy [5] and [6] presented two errorcompensated methods based on two truncation bit groups.…”

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

Chen

2015

IEEE Trans. Circuits Syst. II

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This brief proposes a dynamic error-compensation circuit for a fixed-width squarer based on the Booth folding technique. According the expected value of the partial product through the Booth encoder, a closed form of the compensated value can be derived, including column information that can be used to improve accuracy. The proposed compensation circuit was derived using a mathematical probability model, which means that it is easily implemented for bit-lengths of 32, 64, and longer. Implemented using the TSMC 0.18-µm CMOS process, the proposed 32-bit squarer achieved an operation frequency of 50 MHz and gate count of 3.7 k. Compared with previous solutions, the proposed squarer achieves the best tradeoff between area-efficiency, cost, and accuracy.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

Chen

2015

IEEE Trans. Circuits Syst. II

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“…In [6], [7] the authors propose a truncated squarer with variable correction: the n + 1 th column is added to the n th column and the last n − 1 columns are discarded.…”

Section: Introductionmentioning

confidence: 99%

A novel truncated squarer with linear compensation function

Garofalo

Coppola

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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A truncated binary squarer is a squarer with a n bit input that produces a n bit output. The proposed design minimizes the mean square error of the squarer and results in a very simple and fast circuital implementation.The squarer, compared against state of the art circuits, provides a reduction of the mean square error ranging from 20% to 5%. At the same time, the proposed squarer is able to reduce the power dissipation, reduce the silicon area occupation, and increase the maximum working frequency. Implementations results are provided for a 0.18 µm technology.

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“…Although the squaring operation can be executed using a fixed-width multiplier, redundant circuit areas occur in very large scale integration (VLSI) designs. Thus, many squarers employ the symmetry to reduce partial products [1][2][3] and introduce error-compensated circuits to alleviate truncation errors of the fixed-width squarers [4,5].…”

mentioning

confidence: 99%

Low‐cost fixed‐width squarer by using probability‐compensated circuit

Chen¹

2014

Electron. lett.

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A simple and uniform compensated bias for a fixed-width squarer is proposed. By employing the expected value of truncation parts, truncation errors can be efficiently alleviated. The proposed squarer derives a simple compensated bias and achieves a small area. The results show that the proposed squarer achieves low-cost, high-accuracy performance and yields higher values than previous designs do, particularly regarding the value of accuracy divided by the area-delay product.

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Power and Area Efficient Squarer Design

Cited by 8 publications

References 8 publications

Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

A novel truncated squarer with linear compensation function

Low‐cost fixed‐width squarer by using probability‐compensated circuit

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