A novel truncated squarer with linear compensation function

Garofalo, V.; Coppola, M.; De, Davide; Napoli, Ettore; Petra, Nicola; Strollo, A.G.M.

doi:10.1109/iscas.2010.5537591

Cited by 18 publications

(6 citation statements)

References 9 publications

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“…The FFT unit is a mixed-radix dual-channel unit which operates following a decimation in frequency approach. Internal multiply operation are optimized in terms of speed and HW resource utilization exploiting the circuits and the design techniques proposed in [10][11][12][13]. The output from the FFT is not reordered inside the unit itself to avoid incurring in the associated resource utilization penalty: for this reason, a memory address generator issues to block buffers 1 and 2 the correct sequence of read/write addresses in order to allow the storage of the output data in the natural ordering.…”

Section: Proposed Filtering Processor Architecturementioning

confidence: 99%

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

Lopez

Napoli

Strollo

2015

Lecture Notes in Electrical Engineering

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The Scale Invariant Feature Transform (SIFT) extracts relevant features from images and video frames. The extracted features are robust against luminance variations, geometrical transformations, and image resolution. Due to its performances, the SIFT algorithm is of great importance in fields such as object recognition, content retrieval from image databases, robotic navigation, and gesture recognition. Main drawback of the SIFT algorithm is the high computational complexity. This paper presents the development of a hardware filtering accelerator for the implementation of SIFT-based visual search. The accelerator works in the frequency domain, operating on a block-by-block basis. This enables to work faithfully to the original Scale-Space theory, which employes non-separable Laplacian of Gaussian (LoG) filters. The targeted throughput is of ∼20 fps, making the coprocessor suitable for real time processing.

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Section: Proposed Filtering Processor Architecturementioning

confidence: 99%

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

Lopez

Napoli

Strollo

2015

Lecture Notes in Electrical Engineering

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“…Squaring operations can be executed using a fixed-width multiplier; however, this tends to results in redundant circuitry when dealing with very-large-scale integration (VLSI) designs. Therefore, many squarers employ symmetry to reduce partial products [2]- [3] as well as error-compensation circuits to alleviate the effects of truncation errors associated with fixedwidth squarers [4]- [5]. The Booth-folding technique (BFT) [3] has been shown to reduce 50% of the partial products, compared to a simple folding structure [2].…”

Section: Introductionmentioning

confidence: 99%

“…The Booth-folding technique (BFT) [3] has been shown to reduce 50% of the partial products, compared to a simple folding structure [2]. To reduce area overhead, the truncated fixed-width squarers with errorcompensation circuits for simple folding [4]- [5] and BFT [6] techniques are presented. The merged partial products squarer with an error-compensation circuit presented in [4] has proved a highly efficient design with regard to power usage and area efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…The merged partial products squarer with an error-compensation circuit presented in [4] has proved a highly efficient design with regard to power usage and area efficiency. Linear compensation was proposed with the aim of improving accuracy [5] and [6] presented two errorcompensated methods based on two truncation bit groups. The use of BFT has been shown to enhance accuracy by reducing the number of truncated partial products.…”

Section: Introductionmentioning

confidence: 99%

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Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

Chen

2015

IEEE Trans. Circuits Syst. II

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This brief proposes a dynamic error-compensation circuit for a fixed-width squarer based on the Booth folding technique. According the expected value of the partial product through the Booth encoder, a closed form of the compensated value can be derived, including column information that can be used to improve accuracy. The proposed compensation circuit was derived using a mathematical probability model, which means that it is easily implemented for bit-lengths of 32, 64, and longer. Implemented using the TSMC 0.18-µm CMOS process, the proposed 32-bit squarer achieved an operation frequency of 50 MHz and gate count of 3.7 k. Compared with previous solutions, the proposed squarer achieves the best tradeoff between area-efficiency, cost, and accuracy.

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“…In this context, analog processing performed in focal-plane Vision Systems-on-Chip [20] can represent an interesting choice. Important functions from the perspective of their applications are multiplying/dividing [21][22][23][24][25][26][27][28][29][30], exponential [31][32][33][34], squaring/square-rooting [30,[35][36][37][38][39][40][41], or Euclidean distance [42,43] functions.…”

Section: Introductionmentioning

confidence: 99%

High-accuracy function synthesizer circuit with applications in signal processing

Popa

2012

EURASIP J. Adv. Signal Process.

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An original low-voltage current-mode high-accuracy function synthesizer circuit will be presented, allowing to implement a multitude of continuous mathematical functions. The dynamic range is strongly extended as a result of the superior-order approximation of the implemented functions. The current-mode operation and the independence of the circuit performances on technological parameters are responsible for an additional improvement of structure accuracy. The advantages of reduced design costs per function represent an immediate consequence of the multiple functions realized by the proposed structure. The approximation error of the original function synthesizer circuit is 0.3% for an extended range of the input signal. The function synthesizer is designed for implementing in 0.18 μm CMOS technology and it is supplied at 1 V. An original application of the proposed function synthesizer circuit is represented by a new fourth-order approximation exponential function generator, having a dynamic range of approximately 33 dB, for an error smaller than 1 dB.

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A novel truncated squarer with linear compensation function

Cited by 18 publications

References 9 publications

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

Towards a Frequency Domain Processor for Real-Time SIFT-based Filtering

Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit

High-accuracy function synthesizer circuit with applications in signal processing

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