Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

Bajwa, R.S.; Schumann, N.; Kojima, Hirotsugu

doi:10.1145/263272.263309

Cited by 8 publications

(8 citation statements)

References 9 publications

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“…These are the same benchmarks used to test the processor in Bajwa et al [1997]. Power consumption of the instruction loop buffer (ILB), memories, buses, ALU, the multiplier, and other functional units are collected as the benchmarks are run.…”

Section: Core Power Estimation Datamentioning

confidence: 99%

“…The reason is that the complicated state transitions can be classified by the instruction formats, and output signal transitions can provide more accurate information. The results of our power estimator are compared with the power consumption data provided by Bajwa et al [1997]. Bajwa et al [1997] analyzed the power consumption of the signal processor by performing a switch-level simulation.…”

Section: Introductionmentioning

confidence: 99%

“…The results of our power estimator are compared with the power consumption data provided by Bajwa et al [1997]. Bajwa et al [1997] analyzed the power consumption of the signal processor by performing a switch-level simulation. The simulation platform used is Verilog and the package that worked with it to keep track of the switch capacitance is PowerSim RM .…”

Section: Introductionmentioning

confidence: 99%

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Architecture-level power estimation and design experiments

Chen

Irwin

Bajwa

2001

ACM Trans. Des. Autom. Electron. Syst.

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Architecture-level power estimation has received more attention recently because of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cycle power consumption data of the architecture on the basis of the instruction/data flow stream. To characterize the power dissipation of control units, a novel hierarchical method has been developed. Using this technique, a power estimator is implemented for a commercial processor. The accuracy of the estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark set. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for first-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate the application of the technique. Furthermore, this technique can evaluate various kinds of software to achieve hardware/software codesign for low power.

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Section: Core Power Estimation Datamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Architecture-level power estimation and design experiments

Chen

Irwin

Bajwa

2001

ACM Trans. Des. Autom. Electron. Syst.

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“…EXPERIMENTAL RESULTS Two sets of benchmarks are used to validate our power estimation method for the control units. They are the same benchmarks used to test the processor in [7]. One set includes speech codec and signal processing kernels listed below: e g711 speech codec: 100 samples of real audio data.…”

Section: B Power Estimation For the Cpu And Dsp Control Unitsmentioning

confidence: 99%

“…But, for the complex CPU and DSP control units, the two-level estimation procedure has to be performed by analyzing the instruction format and output transitions. The accuracy of this approach is demonstrated by comparing the power values it produces against measurements made by a gate level power simulator [7] for the same benchmark set. And the results show that our method can efficiently provide accurate estimation data.…”

Section: Introductionmentioning

confidence: 99%

Architectural level hierarchical power estimation of control units

Chen

Irwin²,

Bajwa

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)

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This paper presents a novel technique used to estimate the power dissipation of control units at the architectural level. Based on the instruction stream and output signals of the control units, this approaclh provides accurate power consumption data without any knowledge of their logic structures. It is a top-down hierarchical method which can handle random logic control units as well as ROlM and PLA based control units. The upper-level power estimation analyzes the instructions through their formats, and produces an efflcient energy model for instruction format transitions. Thte lower-level estimation is performed for each instruction format by tracing the transitions of output signals. For simple logic control units, predictable internal signals can be used instead of output signals. We have applied this technique into an architectural level power estimator of a real processor. The accuracy of the estimator is demonstrated by comparing the power values it produces against measurements made by a gate level power simulator for the name benchmark set. The results show that our estimation approach for control units can provide more accurate solution than statistical analysis and is more efflcient than conventional look-up table based methods.

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Improvement of energy-efficiency in off-chip caches by selective prefetching

Jalminger

Stenström

2002

Microprocessors and Microsystems

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Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

Cited by 8 publications

References 9 publications

Architecture-level power estimation and design experiments

Architecture-level power estimation and design experiments

Architectural level hierarchical power estimation of control units

Improvement of energy-efficiency in off-chip caches by selective prefetching

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