Architecture-level power estimation and design experiments

Abstract

Architecture-level power estimation has received more attention recently because of its efficiency. This article presents a technique used to do power analysis of processors at the architecture level. It provides cycle-by-cycle power consumption data of the architecture on the basis of the instruction/data flow stream. To characterize the power dissipation of control units, a novel hierarchical method has been developed. Using this technique, a power estimator is implemented for a commercial processor. The accuracy of the estimator is validated by comparing the power values it produces against measurements made by a gate-level power simulator for the same benchmark set. Our estimation approach is shown to provide very efficient and accurate power analysis at the architecture level. The energy models built for first-pass estimation (such as ALU, MAC unit, register files) are reusable for future architecture design modification. In this article, we demonstrate the application of the technique. Furthermore, this technique can evaluate various kinds of software to achieve hardware/software codesign for low power.

Scaling and Packing on a Chip Multiprocessor

“…A compiler can generate power-aware code [19,44,45]. There are several general power/energy management systems and tools [1,4,5,10].…”

Power-Aware Scheduling for Parallel Security Processors with Analytical Models

“…The cycle-accurate simulator is written in SystemC in which each PE's simulation can be operated at assigned frequencies based on the voltage scaling. The energy consumption models, according to activity types and structure features of the hardware designs [4], are separated into functional units, control logics, memory, and clock distribution trees. Hence, the energy consumptions are weighted with various considerations.…”

Instruction-level power dissipation in the Intel XScale embedded microprocessor

“…al. [5] also describe a microarchitectural scheme for microprocessor power estimation, while [6] describes a detailed microarchitectural power model of the XScale microprocessor core. Microarchitectural power models rely on the availability of detailed knowledge of the internal microarchitecture of a processor.…”