Power Analysis Attack of an AES GPU Implementation

Luo, Chao; Fei, Yunsi; Zhang, Liwei; Ding, A. Adam; Luo, Pei; Mukherjee, Saoni; Kaeli, David

doi:10.1007/s41635-018-0032-7

Cited by 21 publications

(11 citation statements)

References 23 publications

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“…Since more and more devices are connected to the internet, it is highly important to devise effective countermeasures for such a resource constrained environment, where general purpose methods are not applicable. Recently, the awareness of SCAs has increased tremendously such that the cryptographic implementations on graphics processing unit, which are popular for cryptographic accelerators have been analysed against SCAs [116].…”

Section: Side‐channel Security Of Intelligent Sensor Networkmentioning

confidence: 99%

Survey on power analysis attacks and its impact on intelligent sensor networks

Shanmugham

Paramasivam

2018

IET wirel. sens. syst.

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Smart or intelligent sensors are integrated physical units embedded with sensors, processors, and communication devices. The sensors also known as edge nodes form the lower-most tier in the internet of things architecture. These devices rely on cryptographic technique to ensure 'root of trust' for the users. The implementation attacks namely side-channel attacks (SCAs) pose a dangerous threat for the cryptographic implementation in the edge nodes since the attacks are undetectable by nature. Among the different categories of SCAs proposed in the literature, power analysis attacks (PAAs) are vastly studied and widely employed because it can be mounted with relatively inexpensive equipment. In this study, the different categories of PAAs along with the countermeasures are reviewed in detail. The impact of the SCA on the edge nodes is examined along with a case study on medical sensor nodes.

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Section: Side‐channel Security Of Intelligent Sensor Networkmentioning

confidence: 99%

Survey on power analysis attacks and its impact on intelligent sensor networks

Shanmugham

Paramasivam

2018

IET wirel. sens. syst.

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“…Side channel analysis attacks [1] use emanated by-products of an encryption execution, such as power dissipation [2](referred to as PA attacks), electromagnetic (EM) radiation [3], elapsed time [4] and cache hit/miss information [5] to deduce the secret key from cryptographic algorithms. Side channel analysis attacks have shown successful at revealing secret keys from block cipher algorithms, such as AES [6] and Elliptic-curve cryptography [7] running on Application Specific Integrated Circuits (ASICs) [8], embedded processors [9], Graphics Processing Units (GPUs) [10] and Field Programmable Gate Arrays-FPGAs [11].…”

Section: Introductionmentioning

confidence: 99%

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks

2021

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This paper presents UCloD, a novel random clock delay-based robust and scalable countermeasure against recently discovered remote power analysis (RPA) attacks. UCloD deploys very small clock delays (in the picosecond range) generated using the tapped delays lines (TDLs) to mitigate RPA attacks. UCloD provides the most robust countermeasures demonstrated thus far against RPA attacks. RPA attacks use delay sensors, such as Time to Digital Converters (TDC) or Ring Oscillators (ROs) to measure voltage fluctuations occurring in power delivery networks (PDNs) of Field Programmable Gate Arrays (FPGAs). These voltage fluctuations reveal secret information, such as secret keys of cryptographic circuits. The only countermeasure proposed thus far activates ROs to consume significant power and has managed to secure Advanced Encryption Standard (AES) circuits for up to 300,000 encryptions. Using TDLs available in FPGAs, UCloD randomly varies the clock to the cryptographic circuits under attack to induce noise in the adversary's delay sensor(s). We demonstrate correlation power analysis (referred to as CPA) attack resistance of UCloD AES implementations for up to one million encryptions. Compared to an unprotected AES circuit, UCloD implementations have minimal overheads (0.2% Slice LUT overhead and 4.8% Slice register overhead for Xilinx implementations and 0.5% LogicCells overhead for Lattice Semiconductor implementations).

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“…The secret-key is obtained by analyzing the differential information exhibited by the physical property which is used as a side-channel. Attacks have used different physical properties of a system such as time [9,20,41], power consumption [22], memory consumption [13], sound [8] or electromagnetic emissions [29] to leak data.…”

Section: Introductionmentioning

confidence: 99%

A Compiler Assisted Scheduler for Detecting and Mitigating Cache-Based Side Channel Attacks

Khan,

Mururu,

Pande

2020

Preprint

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Detection and mitigation of side channel attacks is a very important problem. Although this is an active area of research, the solutions proposed in the literature have limitations in that they do not work in a real world multi-tenancy setting on servers, have false positives or high overheads limiting their applicability. In this work, we demonstrate a compiler guided scheduler, Biscuit, which detects the cache based side channel attacks for processes scheduled on multi-tenancy server farms with very high accuracy. At the heart of the scheme is the generation and use of a cache miss model which is inserted by the compiler at the entrances of loop nests to predict the underlying cache misses. Such inserted beacons convey the cache miss information to the scheduler at run time which uses it to co-schedule processes such that their combined cache footprint does not exceed the maximum capacity of the last level cache. The scheduled processes are then monitored for actual vs predicted cache misses and when an anomaly is detected, the scheduler performs a binary search to isolate the attacker. We show that Biscuit is able to detect and mitigate Prime+Probe, Flush+Reload, and Flush+Flush attacks on OpenSSL cryptography algorithms with an F-score of 1 and also detect and mitigate degradation of service on vision application suite with an F-score of 0.92. Under no attack scenario, the scheme poses low overheads (up to a maximum of 6%). We believe that due to its ability to deal with multi-tenancy, its attack detection precision, ability to mitigate and low overheads, such a scheme is practicable.

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Power Analysis Attack of an AES GPU Implementation

Cited by 21 publications

References 23 publications

Survey on power analysis attacks and its impact on intelligent sensor networks

Survey on power analysis attacks and its impact on intelligent sensor networks

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks

A Compiler Assisted Scheduler for Detecting and Mitigating Cache-Based Side Channel Attacks

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