UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks

Abstract

This paper presents UCloD, a novel random clock delay-based robust and scalable countermeasure against recently discovered remote power analysis (RPA) attacks. UCloD deploys very small clock delays (in the picosecond range) generated using the tapped delays lines (TDLs) to mitigate RPA attacks. UCloD provides the most robust countermeasures demonstrated thus far against RPA attacks. RPA attacks use delay sensors, such as Time to Digital Converters (TDC) or Ring Oscillators (ROs) to measure voltage fluctuations occurring in power delivery networks (PDNs) of Field Programmable Gate Arrays (FPGAs). These voltage fluctuations reveal secret information, such as secret keys of cryptographic circuits. The only countermeasure proposed thus far activates ROs to consume significant power and has managed to secure Advanced Encryption Standard (AES) circuits for up to 300,000 encryptions. Using TDLs available in FPGAs, UCloD randomly varies the clock to the cryptographic circuits under attack to induce noise in the adversary's delay sensor(s). We demonstrate correlation power analysis (referred to as CPA) attack resistance of UCloD AES implementations for up to one million encryptions. Compared to an unprotected AES circuit, UCloD implementations have minimal overheads (0.2% Slice LUT overhead and 4.8% Slice register overhead for Xilinx implementations and 0.5% LogicCells overhead for Lattice Semiconductor implementations).

Silicon Photomultipliers for Neutrino Telescopes

“…There are already TDC architectures which could arrive to such a resolution, but, at the moment, they suffer from a high use of resources. For instance, a cascade of input delays can create a tapped delay line [68], which will further increase the resolution of the TDCs. Hitherto, tapped delays have been implemented using the fast carry logic of the FPGA slices [69] or the FPGA routing resources [70] with high use of resources, which makes them unsuitable for neutrino telescopes.…”

1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables

“…The sensor signal travelling through the delay line gets delayed due to FPGA voltage fluctuations which is reflected in latch outputs. Latches record '0's during intense voltage fluctuations (explained in [JIP21]) compared to '1's during normal operating conditions. The TDC sensor proposed in [SGMT18] consumed 34 Slices [UJS + 22a].…”

“…The CLKOut is delayed by the number of delay elements in the chosen delay line (e.g., if p th output (0 ≤ p ≤ P − 1) is chosen from the MUX, the signal is delayed by p × τ ). Tapped delay elements are widely used in FPGAs to provide IO delays and can be cascaded to generate a large range of delays [JIP21]. Tapped delay elements can change the delay at run-time.…”

“…We used a compact AES implementation to test the efficacy of detecting small voltage fluctuations. We used the AES circuit used in [SGMT18,JIP21] The key rank results for the proposed 1LUTSensor and a TDC sensor are shown in Figure 30. The Key ranks for 1LUTSensor showed weak convergence to the correct key.…”