Post-Routing Redundant Via Insertion and Line End Extension with Via Density Consideration

Abstract

-Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. However, if the amount of inserted redundant vias is not well controlled, it could violate via density rules and adversely worsen the yield and reliability of the design. In this paper, we first study the problem of redundant via insertion, and present two methods to accelerate a state-ofthe-art approach (which is based on a maximum independent set (MIS) formulation) to solve it. We then consider the problem of simultaneous redundant via insertion and line end extension. We formulate the problem as a maximum weighted independent set (MWIS) problem and modify the accelerated MIS-based approach to solve it. Lastly, we investigate the problem of simultaneous redundant via insertion and line end extension subject to the maximum via density rule, and present a two-stage approach for it. In the first stage, we ignore the maximum via density rule, and enhance the MWIS-based approach to find the set of regions which violate the maximum via density rule after performing simultaneous redundant via insertion and line end extension. In the second stage, excess redundant vias are removed from those violating regions such that after the removal, the maximum via density rule is met while the total amount of redundant vias removed is minimized. This density-aware redundant via removal problem is formulated as a set of zero-one integer linear programming (0-1 ILP) problems each of which can be solved independently without sacrificing the optimality. The superiorities of our approaches are all demonstrated through promising experimental results.

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

“…Different redundant via insertion based on geotopography information is proposed in [42] where a redundant via is tried for each original via in greedy manner. However, as excessive number of vias can even worsen yield, redundant via insertion under via density constraint is required which is addressed in [43] based on the integer linear programming.…”

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

“…Lee et al [21] recently addressed the problem of simultaneously performing redundant-via insertion and line-end extension in the postrouting stage under via-density consideration. Via-density rules constrain the maximum and minimum numbers of vias in each layout area of a pre-defined size.…”

Redundant Vias Insertion for Performance Enhancement in 3D ICs

“…Recently, Lee et al [4] proposed a novel approach for redundant via insertion to improve yield/reliability and manufacturability in traditional 2D ICs under via density constraints. This approach is an extension of conventional via insertion/placement, since it can help to decrease partial or complete via failure due to various reasons (like manufacturing process).…”

“…In this paper, we extend the redundant via insertion in [4] to 3D ICs and propose an approach of redundant via placement/insertion to minimize the total delay for inter-tier or global interconnects. The issue of signal integrity due to the non-uniform impedance characteristics of interconnects is also carefully addressed.…”