Post-process porous silicon for 5G applications

Scheen, Gilles; Tuyaerts, Romain; Rack, Martin; Nyssens, Lucas; Rasson, Jonathan; Nabet, Massinissa; Raskin, Jean‐Pierre

doi:10.1016/j.sse.2019.107719

Cited by 14 publications

(2 citation statements)

References 18 publications

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“…To decrease signal interconnections in photonic and radio frequency (RF) silicon integral circuits (ICs) produced on silicon‐on‐insulator (SOI) structures, high‐resistivity (HR) silicon wafers with a trap‐reach layer (TR) are often used. [ 1 ] However, the cost of such substrates is usually much higher than that of standard Si wafers. Moreover, the quality of large‐diameter HR silicon is still worse than that of Czochralski silicon (Cz‐Si).…”

Section: Introductionmentioning

confidence: 99%

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation

Popov

Tarkov

Tikhonenko

et al. 2021

Physica Status Solidi (a)

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Using nanoscale inclusions of a wide‐band SiC semiconductor and SiO2 dielectric formed in CO+ molecular ion‐implanted (COII) layers allows creating highly resistive regions inside a moderate‐doped silicon substrate. Contrary to the well‐known implanted proton or argon‐ion insulation, where the high resistance is provided by the unstable radiation defect Fermi‐level pinning, such two‐type antidots form a bend of the silicon bandgap on the heteroboundaries around them, similar to the insulating layer in the p−n junction, and guarantee the absence of mobile charge carrier transport at a certain concentration of antidots and working temperatures below 400 K. These insulating regions save their properties even after hard thermal treatment (1400 K). Moreover, a gas blistering suppression is observed for the silicon‐on‐insulator (SOI) wafers with an ultrathin (10–40 nm) buried oxide (BOX). SIMS measurements demonstrate the strong mobile impurity accumulation at the COII region during subsequent thermal treatments.

show abstract

Section: Introductionmentioning

confidence: 99%

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation

Popov

Tarkov

Tikhonenko

et al. 2021

Physica Status Solidi (a)

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“…The use of high-resistivity (several thousand ohm-cm) silicon as a handle wafer is a typical feature of RF-SOI, allowing the RF-SOI to be immune to high power loss and poor electrical isolation while achieving excellent RF performance. [5][6][7][8] Thus, high-resistivity silicon is essential for fabricating RF-SOI devices.…”

mentioning

confidence: 99%

Development of the conductivity type inversion caused by thermal double donors’ formation in p-type high-resistivity silicon

Liu²,

Wei³

et al. 2023

Appl. Phys. Express

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The formation of thermal double donors (TDDs) during the iso-thermal annealing at 450 ℃ in low-oxygen and high-resistivity silicon was quantitatively investigated, and the oxygen related power parameter x for low-oxygen and high-resistivity silicon was obtained. Excessive TDDs formed in the p-type high-resistivity silicon during the devices manufacturing process will invert the conductivity to n-type. A quantitative relationship between the critical wafer start resistivity and oxygen concentration in p-type high-resistivity silicon was obtained, t. The p-type conductivity can be maintained after devices fabrication by controlling the resistivity below the critical resistivity corresponding to the oxygen concentration in p-type high-resistivity silicon.

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FD-SOI and RF-SOI technologies for 5G

Nyssens,

Rack,

Raskin

2024

New Materials and Devices Enabling 5G Applications and Beyond

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Post-process porous silicon for 5G applications

Cited by 14 publications

References 18 publications

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation

Development of the conductivity type inversion caused by thermal double donors’ formation in p-type high-resistivity silicon

FD-SOI and RF-SOI technologies for 5G

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Post-process porous silicon for 5G applications

Cited by 14 publications

References 18 publications

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO+ Ion Implantation

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO+ Ion Implantation

Development of the conductivity type inversion caused by thermal double donors’ formation in p-type high-resistivity silicon

FD-SOI and RF-SOI technologies for 5G

Contact Info

Product

Resources

About

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation

Thermally Robust High‐Resistance Layers on Low‐Resistance Silicon Synthesized by Molecular CO⁺ Ion Implantation