Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

Abstract

Abstract-Positively weighted and negatively weighted bits (posibits, negabits) have been used in the interpretation of 2'scomplement, negative-radix, and binary signed-digit number representation schemes as a way of facilitating the development of efficient arithmetic algorithms for various application domains. In this paper, we show that a more general view of posibits and negabits, along with their mixed use in any combination (using inverse encoding for negabits), unifies a number of diverse implementation schemes, while at the same time making the resultant designs more efficient by avoiding custom or modified hardware elements and restricting the implementation to the use of standard arithmetic cells. Such standard cells have been highly optimized and are continually improving due to their wide applicability. Other practical benefits of our formulation include facilitation of low-voltage and low-power design, again due to the widespread availability of standard cells in variants optimized for low-voltage operation or energy economy. Pedagogical benefits include more intuitive explanations for a number of widely used transformations, such as Booth's recoding and column compression.

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

“…Therefore we reproduce relevant examples (Examples 1 and 3 in Section 2, and Examples 4 -6 in Section 4) from some of the previously published works [12,14], and our corresponding conference paper [15]. Furthermore, we present an efficient method for converting any canonical WBS encoding to any desired two-deep encoding (see Example 7 in Section 4).…”

On-line Decimal Adder with RBCD Representation

“…Furthermore, they perform a decomposition of this representation in order to get an improvement in the sum. This decomposition is based on the treatment of positive and negative bit values (posibits, negabits) [15]. For example, consider a 3-bit number system, where bits in positions 0, and 2 are posibits, and the bit in position 1 is a negabit.…”

Efficient hardware realization of signed arithmetic operation using IEN

“…This extra operation in the signed operation leads to computational delay. For example, 2's complement representation of -5 (1011) is obtained by a complementary operation of +5 (0101) followed by an addition with logic '1'.The need of pre and post computation steps can be avoided using the concept of negatively weighted bits (negabits) [5]. For negabits logic '1' represent arithmetic value -1, where logic '0' represent arithmetic value '0', however negabits concept leads to nonstandard hardware block for realization.…”