Port-Alternated Switch-and-Select Optical Switches

Abstract

We propose and demonstrate a port-alternated switch-and-select architecture for planar waveguide-based optical switches. The proposed architecture reduces the number of intersections on a path, which leads to both small insertion loss and small path dependence. We demonstrate an 8 × 8 optical switch based on the proposed architecture using a silicon photonic platform, which exhibits a fiber-to-fiber insertion loss of 5.7 dB with a crosstalk below −30 dB. We discuss the scalability of the switch, including the propagation and bend losses of the waveguides.

Broadband 32 × 32 Strictly‐Nonblocking Optical Switch on a Multi‐Layer Si3N4‐on‐SOI Platform

“…Table 1 compares the recent demonstrations of large-scale silicon TO switch fabrics. Although the works [21,22] achieve ultra-low crosstalk with the merit of the S&S topology, the port count of these switches is limited to 16 × 16 due to the massive number of waveguide crossings. The work [13] achieves a low-loss 32 × 32 switch chip based on the PILOSS topology.…”

“…[7][8][9][10][11][12][13][14][15] Among them, silicon photonics technology shows great potential for building large-scale integrated optical switches, due to the advantages of low cost, compact size, fast and power-efficient tuning, and complementary metal-oxidesemiconductor (CMOS) compatibility, which are highly demanded in hybrid electro-optic (EO) and all-optical switching networks. [16] Recently, great efforts have been devoted to implementing high-performance large-scale silicon optical switches with a variety of architectures including path-independent insertion-loss (PILOSS), [13,17] Benes, [7][8][9][10] dilated-Benes, [18] double-layernetworks (DLN), [14,19] switch-and-select (S&S), [11,[20][21][22] and crossbar. [5,6] Among them, the highest radix of silicon optical switches reaches 240 × 240 based on silicon MEMS-actuated waveguide crossings arranged in a crossbar architecture.…”

“…Traditional planar silicon waveguide crossings with an insertion loss of ≈0.05 dB [ 7 ] restrict the scalability of the S&S switch fabrics. Recently, an improved S&S fabric called port‐alternated S&S (PA‐S&S) [ 22 ] has been proposed to reduce the path‐dependent insertion loss by reshuffling switch ports and connections to migrate some waveguide crossings from on‐chip to off‐chip. However, there are more SEs in the power‐consuming “ON” state, resulting in significantly increased power consumption.…”

“…The two most widely used switch elements (SEs) in the silicon optical switch chips are Mach-Zehnder interferometers (MZIs) [7][8][9]14,[17][18][19][20][21][22][23] and micro-ring resonators (MRRs) [10][11][12]15,24] actuated by thermo-optic (TO) or EO effects of silicon. MRR-based optical switches show the advantages of low power consumption and compact size, but the wavelength sensitivity increases the control complexity in real applications.…”

Scalable 3D Silicon Optical Switch Based on CLOS Architecture

“…These 3D integration photonic devices are composed of either multiple passive layers [22] or multiple passive layers integrated with another active one [23], but none of them are all active layers. The improved scale and functionality cannot compensate for the increasing cost and fabrication complexity [16,17,24]. A single-chip OPA was recently realized based on a wafer-scale 3D silicon integrated photonic platform.…”