Polyelectrolyte‐Gated Organic Complementary Circuits Operating at Low Power and Voltage

Electric double-layer transistors: a review of recent progress

“…Moreover, the switching speed of short-length transistor (\10 lm) is ultimately limited by the migration of ions within the P(VPA-AA) layer, indicating that downscaling may not make contribution to faster response. Their investigations focusing on P(VPA-AA)-gated OFETs demonstrated that P(VPA-AA) is an attractive electrolyte which can not only effectively form electric double layer at the interface but also avoid the undesired electrochemical doping in the transistors [82,97,98]. In addition, it is well known that the work function of the gate electrodes plays an important role in device performances, by facilitating or preventing charge injection.…”

Aerosol Jet Printed, Sub‐2 V Complementary Circuits Constructed from P‐ and N‐Type Electrolyte Gated Transistors

“…The current versus input voltage plot of the complementary inverter is displayed in Figure 3 b. Complementary inverters consume little static power because the steady state current is always limited by the OFF current of one of the individual transistors. [ 1 ] Indeed, the static currents (when V in = 0 or V in = V DD ) in the circuits were small, approximately 1-10 nA, meaning the static power consumption was less than 10 nW per logic gate. In Figure 3 c, the dynamic action of a typical complementary inverter is demonstrated.…”

“…A SiO 2 (300 nm)/Si wafer with Electrolyte gated transistors (EGTs) are an attractive class of switching devices for printed electronics because they operate at low voltage, have high transconductances (important for gain), and can be fabricated easily on fl exible or stretchable substrates by common printing methods. [1][2][3] In these devices, an elastic gel (or polymer) electrolyte serves as an ultra-high capacitance gate insulator; the large capacitances (∼10 µF/cm 2 ) derive from mobile ions that, upon application of a gate voltage V G , form two dimensional electric double layers (EDLs) at the gate/electrolyte and semiconductor/electrolyte interfaces (i.e., the 2D double-layer charging mode). In the case of ionpermeable semiconductors, ions on the semiconductor side can diffuse into the semiconductor channels and compensate induced charge carriers resulting in reversible three-dimensional electrochemical doping (3D electrochemical mode).…”

“…[ 1 ] Those devices were made using conventional lithography steps. In contrast, all materials employed here, except the Au source and drain electrodes, were printed using electronically functional liquid inks.…”

Reducing contact resistance in ferroelectric organic transistors by buffering the semiconductor/dielectric interface

“…5 A large variety of methods have been successfully proposed thus far for the enhancement of the charge injection from the metal to the conducting channel in OFETs, such as materials engineering for contact electrodes [6][7][8] and inserting layers that can either tune the work function or dope the contact region. [9][10][11] However, charge injection is surprisingly seldom studied in Fe-OFETs, although they have received intensive attention for various non-volatile memory device applications.…”