Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

Abstract

Abstract-This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.

Recent developments in deca-nanometer vertical MOSFETs

“…The DP device is however inherently Ôdrain upÕ. An alternative approach to minimise parasitic bipolar transistor gain for drain-down configurations (source at the top), is to include a poly-SiGe extrinsic source contact [5]. This serves to steepen the profile of minority carriers injected into the parasitic emitter so increasing the base current and reducing the gain.…”

“…This serves to steepen the profile of minority carriers injected into the parasitic emitter so increasing the base current and reducing the gain. A theoretical model for the base current of such a polySiGe emitter has been developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter [5]. The model is equally valid for the parasitic BJT in vertical MOSFETs.…”

“…Notice that the transistor can be considered to operate in either source up, or down modes although not all architectural features are appropriate for bi-directional operation. Specifically we identify the use of a so-called dielectric pocket (DP) to control SCE (source down mode) [2,3], thickened oxide regions, including a novel fillet oxidation (FILOX) overlap process to minimize overlap capacitance [2,4] and the use of polySiGe regions to reduce the emitter efficiency of the PBT (source up mode) [5]. We now consider these concepts, and indicate the expected performance advantage in the ITRS context.…”

Characterisation of CMOS compatible vertical MOSFETs with new architectures through EKV parameter extraction and RF measurement

“…A major advantage of vertical MOSFETs fabricated by implantation and etch techniques is that a low cost process can be used to produce deca-nano channel devices suitable for analogue/RF circuits [1,2]. However, high gate to drain/source capacitances limit the operating frequency range where useful current and power gain can be achieved.…”

“…However, high gate to drain/source capacitances limit the operating frequency range where useful current and power gain can be achieved. In previous research, a local, self-aligned oxidation process known as fillet localised oxidation (FILOX) was demonstrated to address the problem by thickening the oxide in the overlap region [2,3]. This process serves to thicken the oxide in the gate overlap region thus reducing the overlap capacitances both at the pillar top and bottom.…”