Recent developments in deca-nanometer vertical MOSFETs

Abstract

We report simulations and experimental work relating to innovations in the area of ultra short channel vertical transistors. The use of dielectric pockets can mitigate short channel effects of charge sharing and bulk punch-through; thickened oxide regions can minimize parasitic overlap capacitance in source and drain; a narrow band gap, SiGe source can reduce considerably the gain of the parasitic bipolar transistor which is particularly severe in vertical MOSFETs. The work is put into the context of the ITRS roadmap and it is demonstrated that vertical transistors can provide high performance at relaxed lithographic constraints.

Two-dimensional analytical model to characterize novel MOSFET architecture: insulated shallow extension MOSFET

“…The formed oxide layer in the source and drain regions is then substantially removed to expose the substrate in the source and drain regions and to leave a portion of the oxide layer under the gate electrode to form the dielectric pillar (plug) and a channel region between the source and drain regions. Moreover, the integration of dielectric pillars on vertical architecture has also been reported and its fabrication schemes have been discussed in [10][11][12].…”

Lateral channel engineered hetero material insulated shallow extension gate stack (HMISEGAS) MOSFET structure: high performance RF solution for MOS technology

“…In [8], following the well implantation and gate patterning, depression in the S/D region that determines the depth of a dielectric pillar (pocket) was formed using anisotropic plasma etching. Moreover, incorporation of dielectric pillars on vertical architecture has also been reported and its fabrication schemes have been discussed in [19][20][21].…”

A Vertical Thin Film Transistor Based on Low Temperature Technology (T<600oC)

“…But for large area electronics, the equipments are quite different and another way consists to fabricate vertical channel structures. Vertical TFT emerged as a key technology for several reasons (6,7):…”