PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

Abstract

Abstract-Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explicit construction. Their recent inclusion in a 5G communication standard will only spur more research. However, only a couple of ASICs featuring decoders for polar codes were fabricated, and none of them implements a list-based decoding algorithm. In this paper, we present ASIC measurement results for a fabricated 28 nm CMOS chip that implements two different decoders: the first decoder is tailored toward error-correction performance and flexibility. It supports any code rate as well as three different decoding algorithms: successive cancellation (SC), SC flip and SC list (SCL). The flexible decoder can also decode both non-systematic and systematic polar codes. The second decoder targets speed and energy efficiency. We present measurement results for the first silicon-proven SCL decoder, where its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and an energy per bit of 418.3 pJ/bit at a clock frequency of 721 MHz for a supply of 1.3 V. The energy per bit drops down to 178.1 pJ/bit with a more modest clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply voltage of 0.9 V. For the other two operating modes, the energy per bit is shown to be of approximately 95 pJ/bit. The less flexible high-throughput unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of 628 ns for a measured energy per bit of 1.15 pJ/bit at 451 MHz.

A 5.16Gbps decoder ASIC for Polar Code in 16nm FinFET

“…After sorting, the minimum PM will be subtracted from the PM of all list paths and the quantization of PM will be reduced from Q sort to Q P M . Therefore, Q P M of our ASIC is smaller than that of [12].…”

“…Therefore, it is hard to give a precise comparison for these SC decoders in the table. The flexible decoder and [12] run at the same code rate and length, but the former runs with larger list size (L = 8) and can support larger code length. Even though, the area efficiency of flexible decoder is much higher than the scaled result of [12].…”

“…The flexible decoder and [12] run at the same code rate and length, but the former runs with larger list size (L = 8) and can support larger code length. Even though, the area efficiency of flexible decoder is much higher than the scaled result of [12]. As for ultra-reliable decoder, no fabricated ASIC decoder with L = 32 has been reported in literature.…”

“…A couple of ASIC featuring decoders are fabricated in [10]- [12]. The chip presented in [10] implements the SC decoding algorithm; The chip presented in [11] implements the beliefpropagation decoding algorithm.…”

Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes

“…In this comparison, we use the clock cycles as the measurement, instead of the average number of attempts, since the adopting of pipeline architecture. The decoding latency of the SC decoder and the SCL decoder measured as that does in [15] are portrayed as the reference line. The average decoding latency at each E b /N 0 point is obtained by simulating 1 × 10 8 frames.…”