Abstract-We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties which simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared to a loglikelihood domain implementation, requires less irregular and smaller memories. This simplification together with the gains in the metric sorter, lead to 56% to 137% higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large blocklengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.

Abstract-Under successive cancellation (SC) decoding, polar codes are inferior to other codes of similar blocklength in terms of frame error rate. While more sophisticated decoding algorithms such as list-or stack-decoding partially mitigate this performance loss, they suffer from an increase in complexity. In this paper, we describe a new flavor of the SC decoder, called the SC flip decoder. Our algorithm preserves the low memory requirements of the basic SC decoder and adjusts the required decoding effort to the signal quality. In the waterfall region, its average computational complexity is almost as low as that of the SC decoder.

Abstract-We present a hardware architecture and algorithmic improvements for list SC decoding of polar codes. More specifically, we show how to completely avoid copying of the likelihoods, which is algorithmically the most cumbersome part of list SC decoding. The hardware architecture was synthesized for a blocklength of N = 1024 bits and list sizes L = 2, 4 using a UMC 90nm VLSI technology. The resulting decoder can achieve a coded throughput of 181 Mbps at a frequency of 459 MHz.

Deep unfolding is a method of growing popularity that fuses iterative optimization algorithms with tools from neural networks to efficiently solve a range of tasks in machine learning, signal and image processing, and communication systems. This survey summarizes the principle of deep unfolding and discusses its recent use for communication systems with focus on detection and precoding in multi-antenna (MIMO) wireless systems and decoding of error-correcting codes. To showcase the efficacy and generality of deep unfolding, we describe a range of other tasks relevant to communication systems that can be solved using this emerging paradigm. We conclude the survey by outlining a list of open research problems and future research directions.

LoRa is a chirp spread-spectrum modulation developed for the Internet of Things. In this work, we examine the performance of LoRa in the presence of both additive white Gaussian noise and interference from another LoRa user. To this end, we extend an existing interference model, which assumes perfect alignment of the signal of interest and the interference, to the more realistic case where the interfering user is neither chip-nor phase-aligned with the signal of interest and we derive an expression for the error rate. We show that the existing aligned interference model overestimates the effect of interference on the error rate. Moreover, we prove two symmetries in the interfering signal and we derive low-complexity approximate formulas that can significantly reduce the complexity of computing the symbol and frame error rates compared to the complete expression. Finally, we provide numerical simulations to corroborate the theoretical analysis and to verify the accuracy of our proposed approximations. ). layer, which uses an ALOHA-based channel access scheme in which collisions are not explicitly avoided. These collisions lead to same-technology inter-user interference which may ultimately become the capacity-limiting factor in massive IoT scenarios [13]. For this reason, it is of great interest and importance to study the performance of LoRa under sametechnology interference.The authors of [14] present a mathematical network model for LoRa that includes the capture effect, i.e., the fact that a LoRa packet can be correctly decoded even under interference from another LoRa packet. A stochastic geometry framework for modeling the performance of a single gateway LoRa network is used in [15]. An investigation of the latency, collision rate, and throughput for LoRaWAN under duty-cycle restrictions is performed in [16]. Several real-world deployments of LoRa have been tested, but in order to assess the network scalability of LoRaWAN to future network densities that are expected to be orders of magnitude larger, evaluations through network simulators need to be performed. For this reason, the works of [17], [18] added LoRa functionality to the well-known ns-3 network simulator. A simpler Python-based network simulator for the LoRa uplink was first described in [19], and later extended for the LoRa downlink in [20]. The impact of the downlink feedback on LoRa capacity was also studied in [21]. A general overview and performance evaluations of LoRaWAN can be found in [13], [22].The impact of interference coming from different technologies on the performance of the LoRa modulation has received some attention in the literature. Specifically, [23] studies the co-existence of LoRa with IEEE 802.15.4g, while [24] studies the co-existence of LoRa with ultra-narrowband technologies, such as Sigfox. The impact of interference coming from other LoRa nodes has also received some attention. Specifically, the work of [25] extended the simulator of [19] in order to study the impact of imperfect orthogonality between different LoRa spr...

We show that successive cancellation list decoding can be formulated exclusively using log-likelihood ratios. In addition to numerical stability, the log-likelihood ratio based formulation has useful properties which simplify the sorting step involved in successive cancellation list decoding. We propose a hardware architecture of the successive cancellation list decoder in the log-likelihood ratio domain which, compared to a log-likelihood domain implementation, requires less irregular and smaller memories. This simplification together with the gains in the metric sorter, lead to 56% to 137% higher throughput per unit area than other recently proposed architectures. We then evaluate the empirical performance of the CRC-aided successive cancellation list decoder at different list sizes using different CRCs and conclude that it is important to adapt the CRC length to the list size in order to achieve the best error-rate performance of concatenated polar codes. Finally, we synthesize conventional successive cancellation decoders at large block-lengths with the same block-error probability as our proposed CRC-aided successive cancellation list decoders to demonstrate that, while our decoders have slightly lower throughput and larger area, they have a significantly smaller decoding latency.

Full-duplex systems require very strong selfinterference cancellation in order to operate correctly and a significant part of the self-interference signal is due to non-linear effects created by various transceiver impairments. As such, linear cancellation alone is usually not sufficient and sophisticated non-linear cancellation algorithms have been proposed in the literature. In this work, we investigate the use of a neural network as an alternative to the traditional non-linear cancellation method that is based on polynomial basis functions. Measurement results from a full-duplex testbed demonstrate that a small and simple feed-forward neural network canceler works exceptionally well, as it can match the performance of the polynomial non-linear canceler with significantly lower computational complexity.

Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. More constituent codes are recognized in the updated algorithm and dedicated hardware is added to efficiently decode these new constituent codes. We also alter the polar code construction to further decrease the latency and increase the throughput with little to no noticeable effect on error-correction performance. Rate-flexible decoders for polar codes of length 1024 and 2048 are implemented on FPGA. Over the previous work, they are shown to have from 22% to 28% lower latency and 26% to 34% greater throughput when decoding low-rate codes. On 65 nm ASIC CMOS technology, the proposed decoder for a (1024, 512) polar code is shown to compare favorably against the state-of-the-art ASIC decoders. With a clock frequency of 400 MHz and a supply voltage of 0.8 V, it has a latency of 0.41 $\mu$s and an area efficiency of 1.8 Gbps/mm$^2$ for an energy efficiency of 77 pJ/info. bit. At 600 MHz with a supply of 1 V, the latency is reduced to 0.27 $\mu$s and the area efficiency increased to 2.7 Gbps/mm$^2$ at 115 pJ/info. bit.Comment: 8 pages, 10 figures, submitted to Springer J. Signal Process. Sys