Point to point GALS interconnect

Moore, Simon W.; Taylor, G. L.; Mullins, Robert; Robinson, Peter

doi:10.1109/async.2002.1000297

Cited by 84 publications

(54 citation statements)

References 13 publications

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“…Point-to-point interconnects have been implemented to allow asynchronous communication between GALS modules [22]. In [22], interface wrapper circuits are presented for communication between LS modules.…”

Section: Gals Implementationsmentioning

confidence: 99%

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Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.

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Section: Gals Implementationsmentioning

confidence: 99%

“…In [22], interface wrapper circuits are presented for communication between LS modules. The wrapper interface consists of an arbiter and a calibrated delay line.…”

Section: Gals Implementationsmentioning

confidence: 99%

Asynchronous on-chip networks

Amde¹,

Felicijan²,

Efthymiou³

et al. 2006

System-on-Chip: Next Generation Electronics

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“…Numerous NoC architectures adopt a synchronous approach and more recently there have been studies of asynchronous NoC [6,7] which highlight some of the problems with synchronous NoC such as global clock power consumption, clock skew and electromagnetic interference. An asynchronous point-to-point link that can be used for communication has been investigated in [8]. This scheme uses clock pausing techniques to pass data from the synchronous to asynchronous domains.…”

Section: Introductionmentioning

confidence: 99%

Serialized Asynchronous Links for NoC

Valli¹,

Al-Hashimi²,

Yakovlev³

et al. 2008

2008 Design, Automation and Test in Europe

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“…The most likely synchronization paradigm for future chips is GALS (globally asynchronous locally synchronous), with many clocks [4,5,6]. The basic idea is to partition a system into independently clocked modules that are communicating in a self-timed fashion.…”

Section: Introductionmentioning

confidence: 99%