Planar CMOS analog SiPMs: design, modeling, and characterization

Abstract

, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.keywoards-single-photon avalanche diode (SPAD); silicon photomultiplier (SiPM); single-photon sensitivity; photon counting; CMOS technology; SPICE modeling

Application of CMOS Technology to Silicon Photomultiplier Sensors

“…The CMOS technology offers few possibilities of implementing such guard rings [ 19 , 20 , 21 , 22 ]. By way of example, SPAD, SPAD arrays, and SiPM detection structures with several possible layout techniques for the implementation of guard rings were successfully implemented in 800 nm [ 10 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 ], 700 nm [ 31 ], 500 nm [ 32 , 33 ], 350 nm [ 18 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 ], 180 nm [ 47 , 48 , 49 ], 150 nm [ 50 ], 130 nm [ 15 , 51 , 52 , 53 , 54 , 55 ], and 90 nm [ 56 , 57 ] CMOS nodes, and were used to detect single photon signals on the basis of the avalanche breakdown process. Two main limitations of the CMOS technology remain; namely, the higher dark rate and the lower photon detection efficiency with respect to the custom-technology-based conventional SiPMs.…”

Plug Silicon Photomultiplier for the & Imaging PET System: Physics, Technological Challenges and Application to Modern Nuclear Medicine

“…The results of the second structure show that the presence of the STI deteriorates the dark rate up to a factor 8 and confirms previous experiments . These performances are worse that the state of the art SiPMs developed with custom technology, which obtain dark count rates as low as 30 kHz/mm 2 and show that current CMOS technology needs improvements in order to fully accommodate the needs of SiPM sensor development [15,17].…”

“…implementing new design rules accommodating the needs of the sensor, without a perturbation of the transistor development. As an example in [15,17] an additional mask is implemented in order to produce the p-diffusive guard ring. Another way consists of finding innovative approaches for controlling the properties of the diode edge.…”

“…The implementation of SiPM and SPAD sensitive cells in standard CMOS technology allows the combined integration of sensor and read-out electronics on the same device, with a significant reduction of power consumption and simplification of the operational conditions. In recent years a large number of advanced digital imagers and innovative concepts for light detection were proposed on this basis [15][16][17][18].…”

0.16 µm–BCD Silicon Photomultipliers with Sharp Timing Response and Reduced Correlated Noise

“…Commercially-available SiPMs exploit custom fabrication technologies for optimizing their performance. However, efforts are underway to fabricate SiPMs in CMOS [ 7 ] and BCD [ 8 ] technologies, aiming at cost-effective systems-on-chip (SoC) based on SiPM detectors. Finally, digital SiPMs (dSiPMs), where each pixel integrates an active quenching circuit and provides a digital output to on-chip digital processing electronics, have been demonstrated [ 9 ].…”