Placement and Routing for 3-D System-On-Package Designs

Minz, J.R.; Wong, Eric; Pathak, Mohit; Lim, Sung Kyu

doi:10.1109/tcapt.2006.880441

Cited by 17 publications

(5 citation statements)

References 50 publications

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“…Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips. This is a common scenario in 3D package platforms such as TSV-SIP (through silicon via) and HBM [94][95][96][97][98][99][100][101][102][103]. These two categories of thermal management challenges are reviewed in Secs.…”

Section: Thermal Management Challenges In Heterogeneousmentioning

confidence: 99%

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Kim

Ren

Yuksel³

et al. 2020

Journal of Electronic Packaging

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Thermal metamaterials exhibit thermal properties that do not exist in nature but can be rationally designed to offer unique capabilities of controlling heat transfer. Recent advances have demonstrated successful manipulation of conductive heat transfer and led to novel heat guiding structures such as thermal cloaks, concentrators, etc. These advances imply new opportunities to guide heat transfer in complex systems and new packaging approaches as related to thermal management of electronics. Such aspects are important, as trends of electronics packaging toward higher power, higher density, and 2.5D/3D integration are making thermal management even more challenging. While conventional cooling solutions based on large thermal-conductivity materials as well as heat pipes and heat exchangers may dissipate the heat from a source to a sink in a uniform manner, thermal metamaterials could help dissipate the heat in a deterministic manner and avoid thermal crosstalk and local hot spots. This paper reviews recent advances of thermal metamaterials that are potentially relevant to electronics packaging. While providing an overview of the state-of-the-art and critical 2.5D/3D-integrated packaging challenges, this paper also discusses the implications of thermal metamaterials for the future of electronic packaging thermal management. Thermal metamaterials could provide a solution to nontrivial thermal management challenges. Future research will need to take on the new challenges in implementing the thermal metamaterial designs in high-performance heterogeneous packages to continue to advance the state-of-the-art in electronics packaging.

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Section: Thermal Management Challenges In Heterogeneousmentioning

confidence: 99%

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Kim

Ren

Yuksel³

et al. 2020

Journal of Electronic Packaging

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“…Power supply noise-aware floorplanning has been studied in the past [Zhao et al 2002;Minz et al 2006] by the design automation community. The central idea of these works involves two concepts: the first one focuses on creating a low-impedance path to the power supply, and the second involves optimizing onchip decap placement and allocation to suppress inductive noise effects.…”

Section: Related Workmentioning

confidence: 99%

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation

Healy

Mohamood

Lee

et al. 2011

ACM Trans. Des. Autom. Electron. Syst.

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In this article, we propose a design methodology using two complementary techniques to address highfrequency inductive noise in the early design phase of a microprocessor. First, we propose a noise-aware floorplanning technique that uses microarchitectural profile information to create noise-aware floorplans. Second, we present the design of a dynamic inductive-noise controlling mechanism at the microarchitectural level, which limits the on-die current demand within predefined bounds, regardless of the native power and current characteristics of running applications. By dynamically monitoring the access patterns of microarchitectural modules, our mechanism can effectively limit simultaneous switching activity of close-by modules, thereby leveling voltage ringing at local power-pins. Compared to prior art, our di/dt alleviation technique is the first that takes the processor's floorplan, as well as its power-pin distribution, into account to provide a finer-grained control with minimal performance degradation. Based on the evaluation results using 2D floorplans, we show that our techniques can significantly improve inductive noise induced by current demand variation and reduce the average current variability by up to 7 times, with an average performance overhead of 4.0%. In addition, our floorplan reduces the noise margin violations using our noise-aware floorplan by an average of 56.3% while reducing the decap budget by 28%.

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“…Decoupling capacitors (decaps) can be used during placement to reduce the power supply noise [14], [15]. In these works, the resistive and inductive effects of a 3D P/G grid were used to calculate the decap budget for each placed module.…”

Section: B Related Workmentioning

confidence: 99%

Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

Falkenstern

Xie

Chang

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D designs by providing smaller chip areas and higher performance and lower power consumption. However, before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools, the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the floorplan and the P/G network concurrently. Most current 3D IC floorplanners neglect the effects of the 3D P/G network on the design, which may lead to large IR drops in the circuit. To create feasible floorplans with efficient P/G networks, the 3D Floorplan and P/G Co-synthesis tool optimizes the floorplan in terms of wirelength, area and P/G routing area and IR drops. The tool integrates a 3D B*-tree floorplan representation, a resistive P/G mesh, and a Simulated Annealing (SA) engine to explore the 3D floorplan and P/G network. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool show that 3D ICs tend to increase the P/G routing area while decreasing the IR drops in the circuit. By considering the IR drop while floorplanning, exploring the 3D P/G design space, and evaluating 3D IC's effect on 3D P/G networks, the 3D Floorplan and P/G Co-synthesis tool can develop a more efficient 3D IC.

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Placement and Routing for 3-D System-On-Package Designs

Cited by 17 publications

References 50 publications

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation

Three-dimensional integrated circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis

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