Placement Algorithm in Analog-Layout Designs

Zhang, Lihong; Raut, R.; Jiang, Yingtao; Kleine, U.

doi:10.1109/tcad.2005.860957

Cited by 20 publications

(6 citation statements)

References 27 publications

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“…This is why simulated annealing, the most popular of the stochastic techniques, provided the exploration engine for effective placement tools for analog design: ILAC [24], KOAN/ANAGRAM II [7], PUPPY-A [20], LAYLA [14]. More recently, a two-phase approach using both a genetic algorithm and simulated annealing with dynamic adjustment of the parameters has been reported [28]. These software synthesis systems for analog layout approached the device-level placement problems in the traditional way initiated by Jepsen and Gellat for macrocell placement [11], that is, to explore within a combinatorial optimization framework the search space of both feasible and unfeasible solutions.…”

Section: Constraintsmentioning

confidence: 99%

Analog layout synthesis - Recent advances in topological approaches

Graeb

Balasa

Castro-López

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs, B*-trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks.

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Section: Constraintsmentioning

confidence: 99%

Analog layout synthesis - Recent advances in topological approaches

Graeb

Balasa

Castro-López

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…Recently proposed automated analog cell generation [12] and placement tools [13][14][15] are driven by geometric constraints. Parasitic considerations are ignored until postextraction.…”

Section: Performance-driven Layout Optimizationmentioning

confidence: 99%

Performance-driven circuit and layout co-optimization for deep-submicron analog circuits

Chan

Žilić

2009

Analog Integr Circ Sig Process

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The deep sub-micron (DSM) process nodes are increasingly marred by layout-dependent effects. The principal reason preventing layout synthesis during circuit design is the cost of edition, verification and extraction of the intermediate solutions repeatedly. This paper proposes a circuit and layout co-optimization scheme through a novel parasitic model-building scheme that exchanges information between the two flows. A placement-based parasitic estimation method to provide parasitic estimations to schematic optimization tools while retaining their efficiency. Extracted parasitics and simulated performance data are imparted into parasitic macro-devices and performance sensitivities. As proved by experimental results, the flexibility of the parasitic models bridges the efficiency and accuracy void between schematic and physical design optimization to ensure rapid DSM design closure.

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“…Applications include sizing of general analog cells (e.g., OPTIMAN [60], FRIDGE [62], ASTRX/OBLX [61]), op amps (e.g., FASY [21], GBOPCAD [63]), VCOs (e.g., CYCLONE [16]), DS modulators (e.g., [64]) and RF receivers (e.g., ORCA [19]), as well as layout generation (e.g., ILAC [65], KOAN/ANAGRAM [66], LAYLA [67], PUPPY-A [68]). Multiple annealing algorithms can also be executed concurrently, combined with operations commonly found in genetic evolutionary processes, like recombination, to find new points (e.g., ASF [69,70]). …”

Section: Annealingmentioning

confidence: 99%

“…Table 1 lists the properties of the base categories according to their elementary implementation in CAD tools. However, practical implementations can be based on a combination of these fundamental methods, e.g., simulated annealing followed by a traditional unconstrained algorithm [21,64], or a genetic algorithm þ simulated annealing method [70]. Fig.…”

Section: Evolutionmentioning

confidence: 99%