Analog layout synthesis - Recent advances in topological approaches

In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. Yet, most of the layout design is still handmade, essentially because analog designers want to have total control over the different design options, and also, due to the fact that current fully automated generators of analog IC layouts produce solutions which are not yet competitive with the manually crafted ones. The state-of-the-art on analog layout automation that follows reveals that after many years of stagnation, electronic design automation (EDA) market is evolving, creating more efficient and complementary approaches to the existing tools. The chapter starts by addressing the placement problem in EDA, providing a brief overview of the most recent placement tools developed, followed by the presentation of the main references of automatic layout generation tools, and the recent advances in layout-aware analog synthesis approaches. Finally, the available commercial solutions for analog layout automation are outlined.

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“…The major topological constraints for analog placement are device matching, device symmetry and device proximity [1], as presented in Fig. 2.1.…”

Section: Layout Constraintsmentioning

confidence: 99%

State of the Art on Analog Layout Automation

Martins¹,

Lourenço²,

Horta³

2012

Generating Analog IC Layouts With LAYGEN II

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“…Transistors sizes in diodes and inverters are chosen to achieve (at each i inverter output) the scaling factor two times bigger than at output i − 1. Assuming the smallest factors in both stages as α 11 and β 21 , the factors of stages can be represented by Eq. 9 and the final DAC converter factor by Eq.…”

Section: Configurable Current Mirrormentioning

confidence: 99%

“…The blocks are controlled using W sp and W sm words. Subsequent blocks SWITCHES 11 and SWITCHES 12 are used to connect inputs to nodes. A single switch is composed of a CMOS pair of transistors with short channels (to minimise switch resistance) and a less than twice minimal width (to minimise parasitic capacitance in the routing node).…”

Section: Routing Of Arraymentioning

confidence: 99%

“…The development of reconfigurable analog circuits, especially field-programmable analog arrays (FPAA) is nowadays the most current challenge in the VLSI 1 branch of science which follows the trends of miniaturisation and automation [11,14,16,26,47]. Solutions for implementing large-scale programmable circuits prototypes with parameters comparable to these of dedicated analog circuits have been appearing in the last few years [1,3,22,24,30].…”

Section: Introductionmentioning

confidence: 99%

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Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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“…Unfortunately the analogue circuit design process is much more difficult than designing digital circuits, takes a lot of time and produces a high risk source of mistakes. More reasons for solutions using analogue circuit automation methods appear in literature [1][2][3]. There is still no method nor a tool which allow to obtain a final ASIC circuit after providing parameters and specifications.…”

Section: Introductionmentioning

confidence: 99%

SI-Studio – environment for SI circuits design automation

Szczęsny¹,

Naumowicz²,

Handkiewicz³

2012

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. The current work is an answer to the problem of designing switched-current (SI) circuits, which is usually a complex issue in the field of microelectronics. The mentioned task is a source of many mistakes and takes a lot of time for designers, therefore authors of the article decided to propose a software solution. This article presents an environment for design automation of analogue circuits in the switched currents technique. It points out the utility advantages of the described tools, which make the work of a VLSI designer much easier, moreover offering a possibility to parameterise the design process considering power consumption, chip area usage and its working speed. It also presents results of an automatic generation of a filter pair circuit, as well as a DCT circuit -automatically generated with the proposed SI-Studio software tools.

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Analog layout synthesis - Recent advances in topological approaches

Cited by 31 publications

References 23 publications

State of the Art on Analog Layout Automation

State of the Art on Analog Layout Automation

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SI-Studio – environment for SI circuits design automation

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