Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations

Abstract

This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related problem. A conventional method for clocking a large digital system is to use a set of metallic lines organized as a tree. This method is limited by the bandwidth of the clock network. Another limitation of existing solutions is that available skew models do not directly take into account process variations. In order to provide a reliable skew model, and to avoid the frequency limitation, we propose a novel approach that distributes the clock with an H-tree, whose branches are composed of minimum-sized inverters rather than metal. With such a structure, we obtain the highest clocking rate achievable with a given technology. Indeed, clock rates around 1 GHz are possible with a 1.2 m CMOS technology. From the skew modeling standpoint, we derive an analytic expression of the skew between two leaves of the H-tree, which we consider to be the difference in root-to-leaf delay pairs. The skew upper bound obtained has an order of complexity which, with respect to the H-tree size D, is the same as the one that may be derived from the Fisher and Kung model for both side-toside and neighbor-to-neighbor communications, i.e., a (D 2 ), whereas, the Steiglitz and Kugelmass probabilistic model predicts 2(D 2 p Log D). In an H-tree implemented with metallic lines, the leaf-to-leaf skew is obviously bounded by the delay between the root and the leaves. However, with the logic based H-tree proposed in this paper, we arrive at a nonobvious result, which states that the leaf-to-leaf skew grows faster than the root-toleaf delay in presence of a uniform transistor time constant gradient. This paper also proposes generalizations of the skew model to 1) the case of chips in a wafer subject to a smooth, but nonuniform gradient and 2) the case of H-tree configurations mixing logic and interconnections; in this respect, this paper covers the H-tree configurations based on the combination of logic and interconnections.

System development improvements using stackable high-channel-count ultrasound hardware

“…As well in [3], VanScheik et al discuss asynchronously connecting systems. We use an approach much like in [4] by Nekili et. al.…”

Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

“…In order to satisfy such tight timing constraints, the clock signal is required to arrive at precisely the same time at every register on a chip. To achieve equal-delay distribution of the clock signal across a die, symmetric hierarchical structures such as H-trees are utilized, especially in the higher levels of a clock distribution network [2][3][4].…”

Analysis of the impact of process variations on clock skew

“…Xi and Dai [3] considered only global process variations (fast and slow corner combinations for PMOS and NMOS devices) and used global derating factors, thus ignoring the effect of local variations. Finally, authors in [6] included the effect of intrachip, long-range gradient variations in an analytical model of the skew of a pipelined H-tree. As the information regarding the individual position and orientation of a chip on the wafer is lost after wafer dicing, the model derived in [6] may be difficult to apply in practice.…”

“…Finally, authors in [6] included the effect of intrachip, long-range gradient variations in an analytical model of the skew of a pipelined H-tree. As the information regarding the individual position and orientation of a chip on the wafer is lost after wafer dicing, the model derived in [6] may be difficult to apply in practice. Moreover, it is shown in this paper that the usually neglected component of mismatch that is proportional to the inverse of the channel area tends to dominate in DSM technologies.…”