Parameter variations and crosstalk noise effects on high performance H-tree clock distribution networks

Abstract

Controlling the delay and the transition time of the clock signal in the presence of various noise sources, process parameter variations and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (V DD ), temperature, and gate oxide thickness (t ox ) on the delay and the transition time of the clock signal are evaluated. Furthermore, the effects of crosstalk between an H-tree structure and other interconnect wires are investigated. Different scenarios of capacitive coupling along different spatial locations of an H-tree are considered. The effects of coupling on the propagation delay, the transition time, and the waveform shape of the clock signal are demonstrated.

Behavioral Model of Symmetrical Multi-Level T-Tree Interconnects

“…Due to the unceasing increase of the electronic system integration, the modern high-speed electronic equipment meets different technological roadblocks due to the interconnect complexity [10][11][12][13][14][15]. In addition to the investigation on the apparition of electromagnetic interferences (EMI) and electromagnetic compatibility (EMC), many works stating the power loss and the interconnect delay effects for example, in the RF/digital devices were done [6,[16][17][18][19][20][21][22][23]. Because of the undesired interconnection perturbations, it has been evidenced that the interconnect delays of high speed digital IC dominate widely gate delays [5].…”

“…During the data stream transmission, these technological issues can be sources of signal distortions, asynchronous effects of the transmitted analog signals and erroneous symbols. So, intensive researches were performed on the modeling of the interconnect networks in order to predict the signal integrity (SI) [9,[11][12][13][14][15][17][18][19][20][21][22][23][24]. To minimize the cost and energy consumption and also for sharing data and clock signals through multipath circuits can be composed of ICs packaged in different levels this later is fundamental [25][26][27][28].…”

“…To minimize the cost and energy consumption and also for sharing data and clock signals through multipath circuits can be composed of ICs packaged in different levels this later is fundamental [25][26][27][28]. In this optic, different topologies as a typical H-tree interconnect [17,25] were investigated. Figure 1 shows the implementation of the H-tree structure with four levels as a typical surface-layout used in Caltech SCORE [4] and Quicksilver's ACM [8].…”

“…The main advantage of this second order delay model is that it enables to investigate the signal delay with good accuracy even for non-monotone time-domain responses. Till now, most of employed algorithms and modeling methods for computing the transient responses induced by lumped tree mesh networks are calculated from the sum of the estimated polynomial transfer function between the branches of different nodes [17,25,[41][42][43][44][45][46][47][48]. In [48][49][50], more general modeling approach enabling to predict the UWB responses of microstrip interconnections is proposed.…”

“…In Section 2, a general topology of symmetrical T-tree Figure 1. H-tree with four levels [4,8,17,25]. networks consisted of lumped L-cells is analyzed.…”